This is gcc.info, produced by makeinfo version 7.1 from gcc.texi. This file documents the use of the GNU compilers. Copyright © 1988-2024 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with the Invariant Sections being "Funding Free Software", the Front-Cover Texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the license is included in the section entitled "GNU Free Documentation License". (a) The FSF's Front-Cover Text is: A GNU Manual (b) The FSF's Back-Cover Text is: You have freedom to copy and modify this GNU Manual, like GNU software. Copies published by the Free Software Foundation raise funds for GNU development. INFO-DIR-SECTION Software development START-INFO-DIR-ENTRY * gcc: (gcc). The GNU Compiler Collection. * g++: (gcc). The GNU C++ compiler. * gcov: (gcc) Gcov. ‘gcov’--a test coverage program. * gcov-tool: (gcc) Gcov-tool. ‘gcov-tool’--an offline gcda profile processing program. * gcov-dump: (gcc) Gcov-dump. ‘gcov-dump’--an offline gcda and gcno profile dump tool. * lto-dump: (gcc) lto-dump. ‘lto-dump’--Tool for dumping LTO object files. END-INFO-DIR-ENTRY This file documents the use of the GNU compilers. Copyright © 1988-2024 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with the Invariant Sections being "Funding Free Software", the Front-Cover Texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the license is included in the section entitled "GNU Free Documentation License". (a) The FSF's Front-Cover Text is: A GNU Manual (b) The FSF's Back-Cover Text is: You have freedom to copy and modify this GNU Manual, like GNU software. Copies published by the Free Software Foundation raise funds for GNU development.  File: gcc.info, Node: Submodel Options, Next: Spec Files, Prev: Developer Options, Up: Invoking GCC 3.19 Machine-Dependent Options ============================== Each target machine supported by GCC can have its own options--for example, to allow you to compile for a particular processor variant or ABI, or to control optimizations specific to that machine. By convention, the names of machine-specific options start with ‘-m’. Some configurations of the compiler also support additional target-specific options, usually for compatibility with other compilers on the same platform. * Menu: * AArch64 Options:: * Adapteva Epiphany Options:: * AMD GCN Options:: * ARC Options:: * ARM Options:: * AVR Options:: * Blackfin Options:: * C6X Options:: * CRIS Options:: * C-SKY Options:: * Darwin Options:: * DEC Alpha Options:: * eBPF Options:: * FR30 Options:: * FT32 Options:: * FRV Options:: * GNU/Linux Options:: * H8/300 Options:: * HPPA Options:: * IA-64 Options:: * LM32 Options:: * LoongArch Options:: * M32C Options:: * M32R/D Options:: * M680x0 Options:: * MCore Options:: * MicroBlaze Options:: * MIPS Options:: * MMIX Options:: * MN10300 Options:: * Moxie Options:: * MSP430 Options:: * NDS32 Options:: * Nios II Options:: * Nvidia PTX Options:: * OpenRISC Options:: * PDP-11 Options:: * PowerPC Options:: * PRU Options:: * RISC-V Options:: * RL78 Options:: * RS/6000 and PowerPC Options:: * RX Options:: * S/390 and zSeries Options:: * SH Options:: * Solaris 2 Options:: * SPARC Options:: * System V Options:: * V850 Options:: * VAX Options:: * Visium Options:: * VMS Options:: * VxWorks Options:: * x86 Options:: * x86 Windows Options:: * Xstormy16 Options:: * Xtensa Options:: * zSeries Options::  File: gcc.info, Node: AArch64 Options, Next: Adapteva Epiphany Options, Up: Submodel Options 3.19.1 AArch64 Options ---------------------- These options are defined for AArch64 implementations: ‘-mabi=NAME’ Generate code for the specified data model. Permissible values are ‘ilp32’ for SysV-like data model where int, long int and pointers are 32 bits, and ‘lp64’ for SysV-like data model where int is 32 bits, but long int and pointers are 64 bits. The default depends on the specific target configuration. Note that the LP64 and ILP32 ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries. ‘-mbig-endian’ Generate big-endian code. This is the default when GCC is configured for an ‘aarch64_be-*-*’ target. ‘-mgeneral-regs-only’ Generate code which uses only the general-purpose registers. This will prevent the compiler from using floating-point and Advanced SIMD registers but will not impose any restrictions on the assembler. ‘-mlittle-endian’ Generate little-endian code. This is the default when GCC is configured for an ‘aarch64-*-*’ but not an ‘aarch64_be-*-*’ target. ‘-mcmodel=tiny’ Generate code for the tiny code model. The program and its statically defined symbols must be within 1MB of each other. Programs can be statically or dynamically linked. ‘-mcmodel=small’ Generate code for the small code model. The program and its statically defined symbols must be within 4GB of each other. Programs can be statically or dynamically linked. This is the default code model. ‘-mcmodel=large’ Generate code for the large code model. This makes no assumptions about addresses and sizes of sections. Programs can be statically linked only. The ‘-mcmodel=large’ option is incompatible with ‘-mabi=ilp32’, ‘-fpic’ and ‘-fPIC’. ‘-mtp=NAME’ Specify the system register to use as a thread pointer. The valid values are ‘tpidr_el0’, ‘tpidrro_el0’, ‘tpidr_el1’, ‘tpidr_el2’, ‘tpidr_el3’. For backwards compatibility the aliases ‘el0’, ‘el1’, ‘el2’, ‘el3’ are also accepted. The default setting is ‘tpidr_el0’. It is recommended to compile all code intended to interoperate with the same value of this option to avoid accessing a different thread pointer from the wrong exception level. ‘-mstrict-align’ ‘-mno-strict-align’ Avoid or allow generating memory accesses that may not be aligned on a natural object boundary as described in the architecture specification. ‘-momit-leaf-frame-pointer’ ‘-mno-omit-leaf-frame-pointer’ Omit or keep the frame pointer in leaf functions. The former behavior is the default. ‘-mstack-protector-guard=GUARD’ ‘-mstack-protector-guard-reg=REG’ ‘-mstack-protector-guard-offset=OFFSET’ Generate stack protection code using canary at GUARD. Supported locations are ‘global’ for a global canary or ‘sysreg’ for a canary in an appropriate system register. With the latter choice the options ‘-mstack-protector-guard-reg=REG’ and ‘-mstack-protector-guard-offset=OFFSET’ furthermore specify which system register to use as base register for reading the canary, and from what offset from that base register. There is no default register or offset as this is entirely for use within the Linux kernel. ‘-mtls-dialect=desc’ Use TLS descriptors as the thread-local storage mechanism for dynamic accesses of TLS variables. This is the default. ‘-mtls-dialect=traditional’ Use traditional TLS as the thread-local storage mechanism for dynamic accesses of TLS variables. ‘-mtls-size=SIZE’ Specify bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48. This option requires binutils 2.26 or newer. ‘-mfix-cortex-a53-835769’ ‘-mno-fix-cortex-a53-835769’ Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769. This involves inserting a NOP instruction between memory instructions and 64-bit integer multiply-accumulate instructions. ‘-mfix-cortex-a53-843419’ ‘-mno-fix-cortex-a53-843419’ Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419. This erratum workaround is made at link time and this will only pass the corresponding flag to the linker. ‘-mlow-precision-recip-sqrt’ ‘-mno-low-precision-recip-sqrt’ Enable or disable the reciprocal square root approximation. This option only has an effect if ‘-ffast-math’ or ‘-funsafe-math-optimizations’ is used as well. Enabling this reduces precision of reciprocal square root results to about 16 bits for single precision and to 32 bits for double precision. ‘-mlow-precision-sqrt’ ‘-mno-low-precision-sqrt’ Enable or disable the square root approximation. This option only has an effect if ‘-ffast-math’ or ‘-funsafe-math-optimizations’ is used as well. Enabling this reduces precision of square root results to about 16 bits for single precision and to 32 bits for double precision. If enabled, it implies ‘-mlow-precision-recip-sqrt’. ‘-mlow-precision-div’ ‘-mno-low-precision-div’ Enable or disable the division approximation. This option only has an effect if ‘-ffast-math’ or ‘-funsafe-math-optimizations’ is used as well. Enabling this reduces precision of division results to about 16 bits for single precision and to 32 bits for double precision. ‘-mtrack-speculation’ ‘-mno-track-speculation’ Enable or disable generation of additional code to track speculative execution through conditional branches. The tracking state can then be used by the compiler when expanding calls to ‘__builtin_speculation_safe_copy’ to permit a more efficient code sequence to be generated. ‘-moutline-atomics’ ‘-mno-outline-atomics’ Enable or disable calls to out-of-line helpers to implement atomic operations. These helpers will, at runtime, determine if the LSE instructions from ARMv8.1-A can be used; if not, they will use the load/store-exclusive instructions that are present in the base ARMv8.0 ISA. This option is only applicable when compiling for the base ARMv8.0 instruction set. If using a later revision, e.g. ‘-march=armv8.1-a’ or ‘-march=armv8-a+lse’, the ARMv8.1-Atomics instructions will be used directly. The same applies when using ‘-mcpu=’ when the selected cpu supports the ‘lse’ feature. This option is on by default. ‘-march=NAME’ Specify the name of the target architecture and, optionally, one or more feature modifiers. This option has the form ‘-march=ARCH{+[no]FEATURE}*’. The table below summarizes the permissible values for ARCH and the features that they enable by default: ARCH value Architecture Includes by default -------------------------------------------------------------------------- ‘armv8-a’ Armv8-A ‘+fp’, ‘+simd’ ‘armv8.1-a’ Armv8.1-A ‘armv8-a’, ‘+crc’, ‘+lse’, ‘+rdma’ ‘armv8.2-a’ Armv8.2-A ‘armv8.1-a’ ‘armv8.3-a’ Armv8.3-A ‘armv8.2-a’, ‘+pauth’ ‘armv8.4-a’ Armv8.4-A ‘armv8.3-a’, ‘+flagm’, ‘+fp16fml’, ‘+dotprod’ ‘armv8.5-a’ Armv8.5-A ‘armv8.4-a’, ‘+sb’, ‘+ssbs’, ‘+predres’ ‘armv8.6-a’ Armv8.6-A ‘armv8.5-a’, ‘+bf16’, ‘+i8mm’ ‘armv8.7-a’ Armv8.7-A ‘armv8.6-a’, ‘+ls64’ ‘armv8.8-a’ Armv8.8-a ‘armv8.7-a’, ‘+mops’ ‘armv8.9-a’ Armv8.9-a ‘armv8.8-a’ ‘armv9-a’ Armv9-A ‘armv8.5-a’, ‘+sve’, ‘+sve2’ ‘armv9.1-a’ Armv9.1-A ‘armv9-a’, ‘+bf16’, ‘+i8mm’ ‘armv9.2-a’ Armv9.2-A ‘armv9.1-a’, ‘+ls64’ ‘armv9.3-a’ Armv9.3-A ‘armv9.2-a’, ‘+mops’ ‘armv9.4-a’ Armv9.4-A ‘armv9.3-a’ ‘armv8-r’ Armv8-R ‘armv8-r’ The value ‘native’ is available on native AArch64 GNU/Linux and causes the compiler to pick the architecture of the host system. This option has no effect if the compiler is unable to recognize the architecture of the host system, The permissible values for FEATURE are listed in the sub-section on *note ‘-march’ and ‘-mcpu’ Feature Modifiers: aarch64-feature-modifiers. Where conflicting feature modifiers are specified, the right-most feature is used. GCC uses NAME to determine what kind of instructions it can emit when generating assembly code. If ‘-march’ is specified without either of ‘-mtune’ or ‘-mcpu’ also being specified, the code is tuned to perform well across a range of target processors implementing the target architecture. ‘-mtune=NAME’ Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: ‘generic’, ‘cortex-a35’, ‘cortex-a53’, ‘cortex-a55’, ‘cortex-a57’, ‘cortex-a72’, ‘cortex-a73’, ‘cortex-a75’, ‘cortex-a76’, ‘cortex-a76ae’, ‘cortex-a77’, ‘cortex-a65’, ‘cortex-a65ae’, ‘cortex-a34’, ‘cortex-a78’, ‘cortex-a78ae’, ‘cortex-a78c’, ‘ares’, ‘exynos-m1’, ‘emag’, ‘falkor’, ‘neoverse-512tvb’, ‘neoverse-e1’, ‘neoverse-n1’, ‘neoverse-n2’, ‘neoverse-v1’, ‘neoverse-v2’, ‘qdf24xx’, ‘saphira’, ‘phecda’, ‘xgene1’, ‘vulcan’, ‘octeontx’, ‘octeontx81’, ‘octeontx83’, ‘octeontx2’, ‘octeontx2t98’, ‘octeontx2t96’ ‘octeontx2t93’, ‘octeontx2f95’, ‘octeontx2f95n’, ‘octeontx2f95mm’, ‘a64fx’, ‘thunderx’, ‘thunderxt88’, ‘thunderxt88p1’, ‘thunderxt81’, ‘tsv110’, ‘thunderxt83’, ‘thunderx2t99’, ‘thunderx3t110’, ‘zeus’, ‘cortex-a57.cortex-a53’, ‘cortex-a72.cortex-a53’, ‘cortex-a73.cortex-a35’, ‘cortex-a73.cortex-a53’, ‘cortex-a75.cortex-a55’, ‘cortex-a76.cortex-a55’, ‘cortex-r82’, ‘cortex-x1’, ‘cortex-x1c’, ‘cortex-x2’, ‘cortex-x3’, ‘cortex-x4’, ‘cortex-a510’, ‘cortex-a520’, ‘cortex-a710’, ‘cortex-a715’, ‘cortex-a720’, ‘ampere1’, ‘ampere1a’, ‘ampere1b’, ‘cobalt-100’ and ‘native’. The values ‘cortex-a57.cortex-a53’, ‘cortex-a72.cortex-a53’, ‘cortex-a73.cortex-a35’, ‘cortex-a73.cortex-a53’, ‘cortex-a75.cortex-a55’, ‘cortex-a76.cortex-a55’ specify that GCC should tune for a big.LITTLE system. The value ‘neoverse-512tvb’ specifies that GCC should tune for Neoverse cores that (a) implement SVE and (b) have a total vector bandwidth of 512 bits per cycle. In other words, the option tells GCC to tune for Neoverse cores that can execute 4 128-bit Advanced SIMD arithmetic instructions a cycle and that can execute an equivalent number of SVE arithmetic instructions per cycle (2 for 256-bit SVE, 4 for 128-bit SVE). This is more general than tuning for a specific core like Neoverse V1 but is more specific than the default tuning described below. Additionally on native AArch64 GNU/Linux systems the value ‘native’ tunes performance to the host system. This option has no effect if the compiler is unable to recognize the processor of the host system. Where none of ‘-mtune=’, ‘-mcpu=’ or ‘-march=’ are specified, the code is tuned to perform well across a range of target processors. This option cannot be suffixed by feature modifiers. ‘-mcpu=NAME’ Specify the name of the target processor, optionally suffixed by one or more feature modifiers. This option has the form ‘-mcpu=CPU{+[no]FEATURE}*’, where the permissible values for CPU are the same as those available for ‘-mtune’. The permissible values for FEATURE are documented in the sub-section on *note ‘-march’ and ‘-mcpu’ Feature Modifiers: aarch64-feature-modifiers. Where conflicting feature modifiers are specified, the right-most feature is used. GCC uses NAME to determine what kind of instructions it can emit when generating assembly code (as if by ‘-march’) and to determine the target processor for which to tune for performance (as if by ‘-mtune’). Where this option is used in conjunction with ‘-march’ or ‘-mtune’, those options take precedence over the appropriate part of this option. ‘-mcpu=neoverse-512tvb’ is special in that it does not refer to a specific core, but instead refers to all Neoverse cores that (a) implement SVE and (b) have a total vector bandwidth of 512 bits a cycle. Unless overridden by ‘-march’, ‘-mcpu=neoverse-512tvb’ generates code that can run on a Neoverse V1 core, since Neoverse V1 is the first Neoverse core with these properties. Unless overridden by ‘-mtune’, ‘-mcpu=neoverse-512tvb’ tunes code in the same way as for ‘-mtune=neoverse-512tvb’. ‘-moverride=STRING’ Override tuning decisions made by the back-end in response to a ‘-mtune=’ switch. The syntax, semantics, and accepted values for STRING in this option are not guaranteed to be consistent across releases. This option is only intended to be useful when developing GCC. ‘-mverbose-cost-dump’ Enable verbose cost model dumping in the debug dump files. This option is provided for use in debugging the compiler. ‘-mpc-relative-literal-loads’ ‘-mno-pc-relative-literal-loads’ Enable or disable PC-relative literal loads. With this option literal pools are accessed using a single instruction and emitted after each function. This limits the maximum size of functions to 1MB. This is enabled by default for ‘-mcmodel=tiny’. ‘-msign-return-address=SCOPE’ Select the function scope on which return address signing will be applied. Permissible values are ‘none’, which disables return address signing, ‘non-leaf’, which enables pointer signing for functions which are not leaf functions, and ‘all’, which enables pointer signing for all functions. The default value is ‘none’. This option has been deprecated by -mbranch-protection. ‘-mbranch-protection=NONE|STANDARD|PAC-RET[+LEAF+B-KEY]|BTI’ Select the branch protection features to use. ‘none’ is the default and turns off all types of branch protection. ‘standard’ turns on all types of branch protection features. If a feature has additional tuning options, then ‘standard’ sets it to its standard level. ‘pac-ret[+LEAF]’ turns on return address signing to its standard level: signing functions that save the return address to memory (non-leaf functions will practically always do this) using the a-key. The optional argument ‘leaf’ can be used to extend the signing to include leaf functions. The optional argument ‘b-key’ can be used to sign the functions with the B-key instead of the A-key. ‘bti’ turns on branch target identification mechanism. ‘-mharden-sls=OPTS’ Enable compiler hardening against straight line speculation (SLS). OPTS is a comma-separated list of the following options: ‘retbr’ ‘blr’ In addition, ‘-mharden-sls=all’ enables all SLS hardening while ‘-mharden-sls=none’ disables all SLS hardening. ‘-mearly-ra=SCOPE’ Determine when to enable an early register allocation pass. This pass runs before instruction scheduling and tries to find a spill-free allocation of floating-point and vector code. It also tries to make use of strided multi-register instructions, such as SME2's strided LD1 and ST1. The possible values of SCOPE are: ALL, which runs the pass on all functions; STRIDED, which runs the pass on functions that have access to strided multi-register instructions; and NONE, which disables the pass. ‘-mearly-ra=all’ is the default for ‘-O2’ and above, and for ‘-Os’. ‘-mearly-ra=none’ is the default otherwise. ‘-mearly-ldp-fusion’ Enable the copy of the AArch64 load/store pair fusion pass that runs before register allocation. Enabled by default at ‘-O’ and above. ‘-mlate-ldp-fusion’ Enable the copy of the AArch64 load/store pair fusion pass that runs after register allocation. Enabled by default at ‘-O’ and above. ‘-msve-vector-bits=BITS’ Specify the number of bits in an SVE vector register. This option only has an effect when SVE is enabled. GCC supports two forms of SVE code generation: "vector-length agnostic" output that works with any size of vector register and "vector-length specific" output that allows GCC to make assumptions about the vector length when it is useful for optimization reasons. The possible values of ‘bits’ are: ‘scalable’, ‘128’, ‘256’, ‘512’, ‘1024’ and ‘2048’. Specifying ‘scalable’ selects vector-length agnostic output. At present ‘-msve-vector-bits=128’ also generates vector-length agnostic output for big-endian targets. All other values generate vector-length specific code. The behavior of these values may change in future releases and no value except ‘scalable’ should be relied on for producing code that is portable across different hardware SVE vector lengths. The default is ‘-msve-vector-bits=scalable’, which produces vector-length agnostic code. 3.19.1.1 ‘-march’ and ‘-mcpu’ Feature Modifiers ............................................... Feature modifiers used with ‘-march’ and ‘-mcpu’ can be any of the following and their inverses ‘noFEATURE’: ‘crc’ Enable CRC extension. This is on by default for ‘-march=armv8.1-a’. ‘crypto’ Enable Crypto extension. This also enables Advanced SIMD and floating-point instructions. ‘fp’ Enable floating-point instructions. This is on by default for all possible values for options ‘-march’ and ‘-mcpu’. ‘simd’ Enable Advanced SIMD instructions. This also enables floating-point instructions. This is on by default for all possible values for options ‘-march’ and ‘-mcpu’. ‘sve’ Enable Scalable Vector Extension instructions. This also enables Advanced SIMD and floating-point instructions. ‘lse’ Enable Large System Extension instructions. This is on by default for ‘-march=armv8.1-a’. ‘rdma’ Enable Round Double Multiply Accumulate instructions. This is on by default for ‘-march=armv8.1-a’. ‘fp16’ Enable FP16 extension. This also enables floating-point instructions. ‘fp16fml’ Enable FP16 fmla extension. This also enables FP16 extensions and floating-point instructions. This option is enabled by default for ‘-march=armv8.4-a’. Use of this option with architectures prior to Armv8.2-A is not supported. ‘rcpc’ Enable the RCpc extension. This enables the use of the LDAPR instructions for load-acquire atomic semantics, and passes it on to the assembler, enabling inline asm statements to use instructions from the RCpc extension. ‘dotprod’ Enable the Dot Product extension. This also enables Advanced SIMD instructions. ‘aes’ Enable the Armv8-a aes and pmull crypto extension. This also enables Advanced SIMD instructions. ‘sha2’ Enable the Armv8-a sha2 crypto extension. This also enables Advanced SIMD instructions. ‘sha3’ Enable the sha512 and sha3 crypto extension. This also enables Advanced SIMD instructions. Use of this option with architectures prior to Armv8.2-A is not supported. ‘sm4’ Enable the sm3 and sm4 crypto extension. This also enables Advanced SIMD instructions. Use of this option with architectures prior to Armv8.2-A is not supported. ‘profile’ Enable the Statistical Profiling extension. This option is only to enable the extension at the assembler level and does not affect code generation. ‘rng’ Enable the Armv8.5-a Random Number instructions. This option is only to enable the extension at the assembler level and does not affect code generation. ‘memtag’ Enable the Armv8.5-a Memory Tagging Extensions. Use of this option with architectures prior to Armv8.5-A is not supported. ‘sb’ Enable the Armv8-a Speculation Barrier instruction. This option is only to enable the extension at the assembler level and does not affect code generation. This option is enabled by default for ‘-march=armv8.5-a’. ‘ssbs’ Enable the Armv8-a Speculative Store Bypass Safe instruction. This option is only to enable the extension at the assembler level and does not affect code generation. This option is enabled by default for ‘-march=armv8.5-a’. ‘predres’ Enable the Armv8-a Execution and Data Prediction Restriction instructions. This option is only to enable the extension at the assembler level and does not affect code generation. This option is enabled by default for ‘-march=armv8.5-a’. ‘sve2’ Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE instructions. ‘sve2-bitperm’ Enable SVE2 bitperm instructions. This also enables SVE2 instructions. ‘sve2-sm4’ Enable SVE2 sm4 instructions. This also enables SVE2 instructions. ‘sve2-aes’ Enable SVE2 aes instructions. This also enables SVE2 instructions. ‘sve2-sha3’ Enable SVE2 sha3 instructions. This also enables SVE2 instructions. ‘tme’ Enable the Transactional Memory Extension. ‘i8mm’ Enable 8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions. This option is enabled by default for ‘-march=armv8.6-a’. Use of this option with architectures prior to Armv8.2-A is not supported. ‘f32mm’ Enable 32-bit Floating point Matrix Multiply instructions. This also enables SVE instructions. Use of this option with architectures prior to Armv8.2-A is not supported. ‘f64mm’ Enable 64-bit Floating point Matrix Multiply instructions. This also enables SVE instructions. Use of this option with architectures prior to Armv8.2-A is not supported. ‘bf16’ Enable brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions. This option is enabled by default for ‘-march=armv8.6-a’. Use of this option with architectures prior to Armv8.2-A is not supported. ‘ls64’ Enable the 64-byte atomic load and store instructions for accelerators. This option is enabled by default for ‘-march=armv8.7-a’. ‘mops’ Enable the instructions to accelerate memory operations like ‘memcpy’, ‘memmove’, ‘memset’. This option is enabled by default for ‘-march=armv8.8-a’ ‘flagm’ Enable the Flag Manipulation instructions Extension. ‘pauth’ Enable the Pointer Authentication Extension. ‘cssc’ Enable the Common Short Sequence Compression instructions. ‘sme’ Enable the Scalable Matrix Extension. ‘sme-i16i64’ Enable the FEAT_SME_I16I64 extension to SME. ‘sme-f64f64’ Enable the FEAT_SME_F64F64 extension to SME. + ‘sme2’ Enable the Scalable Matrix Extension 2. This also enables SME instructions. ‘d128’ Enable support for 128-bit system register read/write instructions. ‘gcs’ Enable support for Armv9.4-a Guarded Control Stack extension. ‘the’ Enable support for Armv8.9-a/9.4-a translation hardening extension. ‘rcpc3’ Enable the RCpc3 (Release Consistency) extension. Feature ‘crypto’ implies ‘aes’, ‘sha2’, and ‘simd’, which implies ‘fp’. Conversely, ‘nofp’ implies ‘nosimd’, which implies ‘nocrypto’, ‘noaes’ and ‘nosha2’.  File: gcc.info, Node: Adapteva Epiphany Options, Next: AMD GCN Options, Prev: AArch64 Options, Up: Submodel Options 3.19.2 Adapteva Epiphany Options -------------------------------- These ‘-m’ options are defined for Adapteva Epiphany: ‘-mhalf-reg-file’ Don't allocate any register in the range ‘r32’...‘r63’. That allows code to run on hardware variants that lack these registers. ‘-mprefer-short-insn-regs’ Preferentially allocate registers that allow short instruction generation. This can result in increased instruction count, so this may either reduce or increase overall code size. ‘-mbranch-cost=NUM’ Set the cost of branches to roughly NUM "simple" instructions. This cost is only a heuristic and is not guaranteed to produce consistent results across releases. ‘-mcmove’ Enable the generation of conditional moves. ‘-mnops=NUM’ Emit NUM NOPs before every other generated instruction. ‘-mno-soft-cmpsf’ For single-precision floating-point comparisons, emit an ‘fsub’ instruction and test the flags. This is faster than a software comparison, but can get incorrect results in the presence of NaNs, or when two different small numbers are compared such that their difference is calculated as zero. The default is ‘-msoft-cmpsf’, which uses slower, but IEEE-compliant, software comparisons. ‘-mstack-offset=NUM’ Set the offset between the top of the stack and the stack pointer. E.g., a value of 8 means that the eight bytes in the range ‘sp+0...sp+7’ can be used by leaf functions without stack allocation. Values other than ‘8’ or ‘16’ are untested and unlikely to work. Note also that this option changes the ABI; compiling a program with a different stack offset than the libraries have been compiled with generally does not work. This option can be useful if you want to evaluate if a different stack offset would give you better code, but to actually use a different stack offset to build working programs, it is recommended to configure the toolchain with the appropriate ‘--with-stack-offset=NUM’ option. ‘-mno-round-nearest’ Make the scheduler assume that the rounding mode has been set to truncating. The default is ‘-mround-nearest’. ‘-mlong-calls’ If not otherwise specified by an attribute, assume all calls might be beyond the offset range of the ‘b’ / ‘bl’ instructions, and therefore load the function address into a register before performing a (otherwise direct) call. This is the default. ‘-mshort-calls’ If not otherwise specified by an attribute, assume all direct calls are in the range of the ‘b’ / ‘bl’ instructions, so use these instructions for direct calls. The default is ‘-mlong-calls’. ‘-msmall16’ Assume addresses can be loaded as 16-bit unsigned values. This does not apply to function addresses for which ‘-mlong-calls’ semantics are in effect. ‘-mfp-mode=MODE’ Set the prevailing mode of the floating-point unit. This determines the floating-point mode that is provided and expected at function call and return time. Making this mode match the mode you predominantly need at function start can make your programs smaller and faster by avoiding unnecessary mode switches. MODE can be set to one the following values: ‘caller’ Any mode at function entry is valid, and retained or restored when the function returns, and when it calls other functions. This mode is useful for compiling libraries or other compilation units you might want to incorporate into different programs with different prevailing FPU modes, and the convenience of being able to use a single object file outweighs the size and speed overhead for any extra mode switching that might be needed, compared with what would be needed with a more specific choice of prevailing FPU mode. ‘truncate’ This is the mode used for floating-point calculations with truncating (i.e. round towards zero) rounding mode. That includes conversion from floating point to integer. ‘round-nearest’ This is the mode used for floating-point calculations with round-to-nearest-or-even rounding mode. ‘int’ This is the mode used to perform integer calculations in the FPU, e.g. integer multiply, or integer multiply-and-accumulate. The default is ‘-mfp-mode=caller’ ‘-mno-split-lohi’ ‘-mno-postinc’ ‘-mno-postmodify’ Code generation tweaks that disable, respectively, splitting of 32-bit loads, generation of post-increment addresses, and generation of post-modify addresses. The defaults are ‘msplit-lohi’, ‘-mpost-inc’, and ‘-mpost-modify’. ‘-mnovect-double’ Change the preferred SIMD mode to SImode. The default is ‘-mvect-double’, which uses DImode as preferred SIMD mode. ‘-max-vect-align=NUM’ The maximum alignment for SIMD vector mode types. NUM may be 4 or 8. The default is 8. Note that this is an ABI change, even though many library function interfaces are unaffected if they don't use SIMD vector modes in places that affect size and/or alignment of relevant types. ‘-msplit-vecmove-early’ Split vector moves into single word moves before reload. In theory this can give better register allocation, but so far the reverse seems to be generally the case. ‘-m1reg-REG’ Specify a register to hold the constant −1, which makes loading small negative constants and certain bitmasks faster. Allowable values for REG are ‘r43’ and ‘r63’, which specify use of that register as a fixed register, and ‘none’, which means that no register is used for this purpose. The default is ‘-m1reg-none’.  File: gcc.info, Node: AMD GCN Options, Next: ARC Options, Prev: Adapteva Epiphany Options, Up: Submodel Options 3.19.3 AMD GCN Options ---------------------- These options are defined specifically for the AMD GCN port. ‘-march=GPU’ ‘-mtune=GPU’ Set architecture type or tuning for GPU. Supported values for GPU are ‘fiji’ Compile for GCN3 Fiji devices (gfx803). Support deprecated; availablility depends on how GCC has been configured, see ‘--with-arch’ and ‘--with-multilib-list’. ‘gfx900’ Compile for GCN5 Vega 10 devices (gfx900). ‘gfx906’ Compile for GCN5 Vega 20 devices (gfx906). ‘gfx908’ Compile for CDNA1 Instinct MI100 series devices (gfx908). ‘gfx90a’ Compile for CDNA2 Instinct MI200 series devices (gfx90a). ‘gfx1030’ Compile for RDNA2 gfx1030 devices (GFX10 series). ‘gfx1100’ Compile for RDNA3 gfx1100 devices (GFX11 series). ‘-msram-ecc=on’ ‘-msram-ecc=off’ ‘-msram-ecc=any’ Compile binaries suitable for devices with the SRAM-ECC feature enabled, disabled, or either mode. This feature can be enabled per-process on some devices. The compiled code must match the device mode. The default is ‘any’, for devices that support it. ‘-mstack-size=BYTES’ Specify how many BYTES of stack space will be requested for each GPU thread (wave-front). Beware that there may be many threads and limited memory available. The size of the stack allocation may also have an impact on run-time performance. The default is 32KB when using OpenACC or OpenMP, and 1MB otherwise. ‘-mxnack=on’ ‘-mxnack=off’ ‘-mxnack=any’ Compile binaries suitable for devices with the XNACK feature enabled, disabled, or either mode. Some devices always require XNACK and some allow the user to configure XNACK. The compiled code must match the device mode. The default is ‘-mxnack=any’ on devices that support Unified Shared Memory, and ‘-mxnack=no’ otherwise.  File: gcc.info, Node: ARC Options, Next: ARM Options, Prev: AMD GCN Options, Up: Submodel Options 3.19.4 ARC Options ------------------ The following options control the architecture variant for which code is being compiled: ‘-mbarrel-shifter’ Generate instructions supported by barrel shifter. This is the default unless ‘-mcpu=ARC601’ or ‘-mcpu=ARCEM’ is in effect. ‘-mjli-always’ Force to call a function using jli_s instruction. This option is valid only for ARCv2 architecture. ‘-mcpu=CPU’ Set architecture type, register usage, and instruction scheduling parameters for CPU. There are also shortcut alias options available for backward compatibility and convenience. Supported values for CPU are ‘arc600’ Compile for ARC600. Aliases: ‘-mA6’, ‘-mARC600’. ‘arc601’ Compile for ARC601. Alias: ‘-mARC601’. ‘arc700’ Compile for ARC700. Aliases: ‘-mA7’, ‘-mARC700’. This is the default when configured with ‘--with-cpu=arc700’. ‘arcem’ Compile for ARC EM. ‘archs’ Compile for ARC HS. ‘em’ Compile for ARC EM CPU with no hardware extensions. ‘em4’ Compile for ARC EM4 CPU. ‘em4_dmips’ Compile for ARC EM4 DMIPS CPU. ‘em4_fpus’ Compile for ARC EM4 DMIPS CPU with the single-precision floating-point extension. ‘em4_fpuda’ Compile for ARC EM4 DMIPS CPU with single-precision floating-point and double assist instructions. ‘hs’ Compile for ARC HS CPU with no hardware extensions except the atomic instructions. ‘hs34’ Compile for ARC HS34 CPU. ‘hs38’ Compile for ARC HS38 CPU. ‘hs38_linux’ Compile for ARC HS38 CPU with all hardware extensions on. ‘hs4x’ Compile for ARC HS4x CPU. ‘hs4xd’ Compile for ARC HS4xD CPU. ‘hs4x_rel31’ Compile for ARC HS4x CPU release 3.10a. ‘arc600_norm’ Compile for ARC 600 CPU with ‘norm’ instructions enabled. ‘arc600_mul32x16’ Compile for ARC 600 CPU with ‘norm’ and 32x16-bit multiply instructions enabled. ‘arc600_mul64’ Compile for ARC 600 CPU with ‘norm’ and ‘mul64’-family instructions enabled. ‘arc601_norm’ Compile for ARC 601 CPU with ‘norm’ instructions enabled. ‘arc601_mul32x16’ Compile for ARC 601 CPU with ‘norm’ and 32x16-bit multiply instructions enabled. ‘arc601_mul64’ Compile for ARC 601 CPU with ‘norm’ and ‘mul64’-family instructions enabled. ‘nps400’ Compile for ARC 700 on NPS400 chip. ‘em_mini’ Compile for ARC EM minimalist configuration featuring reduced register set. ‘-mdpfp’ ‘-mdpfp-compact’ Generate double-precision FPX instructions, tuned for the compact implementation. ‘-mdpfp-fast’ Generate double-precision FPX instructions, tuned for the fast implementation. ‘-mno-dpfp-lrsr’ Disable ‘lr’ and ‘sr’ instructions from using FPX extension aux registers. ‘-mea’ Generate extended arithmetic instructions. Currently only ‘divaw’, ‘adds’, ‘subs’, and ‘sat16’ are supported. Only valid for ‘-mcpu=ARC700’. ‘-mno-mpy’ Do not generate ‘mpy’-family instructions for ARC700. This option is deprecated. ‘-mmul32x16’ Generate 32x16-bit multiply and multiply-accumulate instructions. ‘-mmul64’ Generate ‘mul64’ and ‘mulu64’ instructions. Only valid for ‘-mcpu=ARC600’. ‘-mnorm’ Generate ‘norm’ instructions. This is the default if ‘-mcpu=ARC700’ is in effect. ‘-mspfp’ ‘-mspfp-compact’ Generate single-precision FPX instructions, tuned for the compact implementation. ‘-mspfp-fast’ Generate single-precision FPX instructions, tuned for the fast implementation. ‘-msimd’ Enable generation of ARC SIMD instructions via target-specific builtins. Only valid for ‘-mcpu=ARC700’. ‘-msoft-float’ This option ignored; it is provided for compatibility purposes only. Software floating-point code is emitted by default, and this default can overridden by FPX options; ‘-mspfp’, ‘-mspfp-compact’, or ‘-mspfp-fast’ for single precision, and ‘-mdpfp’, ‘-mdpfp-compact’, or ‘-mdpfp-fast’ for double precision. ‘-mswap’ Generate ‘swap’ instructions. ‘-matomic’ This enables use of the locked load/store conditional extension to implement atomic memory built-in functions. Not available for ARC 6xx or ARC EM cores. ‘-mdiv-rem’ Enable ‘div’ and ‘rem’ instructions for ARCv2 cores. ‘-mcode-density’ Enable code density instructions for ARC EM. This option is on by default for ARC HS. ‘-mll64’ Enable double load/store operations for ARC HS cores. ‘-mtp-regno=REGNO’ Specify thread pointer register number. ‘-mmpy-option=MULTO’ Compile ARCv2 code with a multiplier design option. You can specify the option using either a string or numeric value for MULTO. ‘wlh1’ is the default value. The recognized values are: ‘0’ ‘none’ No multiplier available. ‘1’ ‘w’ 16x16 multiplier, fully pipelined. The following instructions are enabled: ‘mpyw’ and ‘mpyuw’. ‘2’ ‘wlh1’ 32x32 multiplier, fully pipelined (1 stage). The following instructions are additionally enabled: ‘mpy’, ‘mpyu’, ‘mpym’, ‘mpymu’, and ‘mpy_s’. ‘3’ ‘wlh2’ 32x32 multiplier, fully pipelined (2 stages). The following instructions are additionally enabled: ‘mpy’, ‘mpyu’, ‘mpym’, ‘mpymu’, and ‘mpy_s’. ‘4’ ‘wlh3’ Two 16x16 multipliers, blocking, sequential. The following instructions are additionally enabled: ‘mpy’, ‘mpyu’, ‘mpym’, ‘mpymu’, and ‘mpy_s’. ‘5’ ‘wlh4’ One 16x16 multiplier, blocking, sequential. The following instructions are additionally enabled: ‘mpy’, ‘mpyu’, ‘mpym’, ‘mpymu’, and ‘mpy_s’. ‘6’ ‘wlh5’ One 32x4 multiplier, blocking, sequential. The following instructions are additionally enabled: ‘mpy’, ‘mpyu’, ‘mpym’, ‘mpymu’, and ‘mpy_s’. ‘7’ ‘plus_dmpy’ ARC HS SIMD support. ‘8’ ‘plus_macd’ ARC HS SIMD support. ‘9’ ‘plus_qmacw’ ARC HS SIMD support. This option is only available for ARCv2 cores. ‘-mfpu=FPU’ Enables support for specific floating-point hardware extensions for ARCv2 cores. Supported values for FPU are: ‘fpus’ Enables support for single-precision floating-point hardware extensions. ‘fpud’ Enables support for double-precision floating-point hardware extensions. The single-precision floating-point extension is also enabled. Not available for ARC EM. ‘fpuda’ Enables support for double-precision floating-point hardware extensions using double-precision assist instructions. The single-precision floating-point extension is also enabled. This option is only available for ARC EM. ‘fpuda_div’ Enables support for double-precision floating-point hardware extensions using double-precision assist instructions. The single-precision floating-point, square-root, and divide extensions are also enabled. This option is only available for ARC EM. ‘fpuda_fma’ Enables support for double-precision floating-point hardware extensions using double-precision assist instructions. The single-precision floating-point and fused multiply and add hardware extensions are also enabled. This option is only available for ARC EM. ‘fpuda_all’ Enables support for double-precision floating-point hardware extensions using double-precision assist instructions. All single-precision floating-point hardware extensions are also enabled. This option is only available for ARC EM. ‘fpus_div’ Enables support for single-precision floating-point, square-root and divide hardware extensions. ‘fpud_div’ Enables support for double-precision floating-point, square-root and divide hardware extensions. This option includes option ‘fpus_div’. Not available for ARC EM. ‘fpus_fma’ Enables support for single-precision floating-point and fused multiply and add hardware extensions. ‘fpud_fma’ Enables support for double-precision floating-point and fused multiply and add hardware extensions. This option includes option ‘fpus_fma’. Not available for ARC EM. ‘fpus_all’ Enables support for all single-precision floating-point hardware extensions. ‘fpud_all’ Enables support for all single- and double-precision floating-point hardware extensions. Not available for ARC EM. ‘-mirq-ctrl-saved=REGISTER-RANGE, BLINK, LP_COUNT’ Specifies general-purposes registers that the processor automatically saves/restores on interrupt entry and exit. REGISTER-RANGE is specified as two registers separated by a dash. The register range always starts with ‘r0’, the upper limit is ‘fp’ register. BLINK and LP_COUNT are optional. This option is only valid for ARC EM and ARC HS cores. ‘-mrgf-banked-regs=NUMBER’ Specifies the number of registers replicated in second register bank on entry to fast interrupt. Fast interrupts are interrupts with the highest priority level P0. These interrupts save only PC and STATUS32 registers to avoid memory transactions during interrupt entry and exit sequences. Use this option when you are using fast interrupts in an ARC V2 family processor. Permitted values are 4, 8, 16, and 32. ‘-mlpc-width=WIDTH’ Specify the width of the ‘lp_count’ register. Valid values for WIDTH are 8, 16, 20, 24, 28 and 32 bits. The default width is fixed to 32 bits. If the width is less than 32, the compiler does not attempt to transform loops in your program to use the zero-delay loop mechanism unless it is known that the ‘lp_count’ register can hold the required loop-counter value. Depending on the width specified, the compiler and run-time library might continue to use the loop mechanism for various needs. This option defines macro ‘__ARC_LPC_WIDTH__’ with the value of WIDTH. ‘-mrf16’ This option instructs the compiler to generate code for a 16-entry register file. This option defines the ‘__ARC_RF16__’ preprocessor macro. ‘-mbranch-index’ Enable use of ‘bi’ or ‘bih’ instructions to implement jump tables. The following options are passed through to the assembler, and also define preprocessor macro symbols. ‘-mdsp-packa’ Passed down to the assembler to enable the DSP Pack A extensions. Also sets the preprocessor symbol ‘__Xdsp_packa’. This option is deprecated. ‘-mdvbf’ Passed down to the assembler to enable the dual Viterbi butterfly extension. Also sets the preprocessor symbol ‘__Xdvbf’. This option is deprecated. ‘-mlock’ Passed down to the assembler to enable the locked load/store conditional extension. Also sets the preprocessor symbol ‘__Xlock’. ‘-mmac-d16’ Passed down to the assembler. Also sets the preprocessor symbol ‘__Xxmac_d16’. This option is deprecated. ‘-mmac-24’ Passed down to the assembler. Also sets the preprocessor symbol ‘__Xxmac_24’. This option is deprecated. ‘-mrtsc’ Passed down to the assembler to enable the 64-bit time-stamp counter extension instruction. Also sets the preprocessor symbol ‘__Xrtsc’. This option is deprecated. ‘-mswape’ Passed down to the assembler to enable the swap byte ordering extension instruction. Also sets the preprocessor symbol ‘__Xswape’. ‘-mtelephony’ Passed down to the assembler to enable dual- and single-operand instructions for telephony. Also sets the preprocessor symbol ‘__Xtelephony’. This option is deprecated. ‘-mxy’ Passed down to the assembler to enable the XY memory extension. Also sets the preprocessor symbol ‘__Xxy’. The following options control how the assembly code is annotated: ‘-misize’ Annotate assembler instructions with estimated addresses. ‘-mannotate-align’ Does nothing. Preserved for backward compatibility. The following options are passed through to the linker: ‘-marclinux’ Passed through to the linker, to specify use of the ‘arclinux’ emulation. This option is enabled by default in tool chains built for ‘arc-linux-uclibc’ and ‘arceb-linux-uclibc’ targets when profiling is not requested. ‘-marclinux_prof’ Passed through to the linker, to specify use of the ‘arclinux_prof’ emulation. This option is enabled by default in tool chains built for ‘arc-linux-uclibc’ and ‘arceb-linux-uclibc’ targets when profiling is requested. The following options control the semantics of generated code: ‘-mlong-calls’ Generate calls as register indirect calls, thus providing access to the full 32-bit address range. ‘-mmedium-calls’ Don't use less than 25-bit addressing range for calls, which is the offset available for an unconditional branch-and-link instruction. Conditional execution of function calls is suppressed, to allow use of the 25-bit range, rather than the 21-bit range with conditional branch-and-link. This is the default for tool chains built for ‘arc-linux-uclibc’ and ‘arceb-linux-uclibc’ targets. ‘-G NUM’ Put definitions of externally-visible data in a small data section if that data is no bigger than NUM bytes. The default value of NUM is 4 for any ARC configuration, or 8 when we have double load/store operations. ‘-mno-sdata’ Do not generate sdata references. This is the default for tool chains built for ‘arc-linux-uclibc’ and ‘arceb-linux-uclibc’ targets. ‘-mvolatile-cache’ Use ordinarily cached memory accesses for volatile references. This is the default. ‘-mno-volatile-cache’ Enable cache bypass for volatile references. The following options fine tune code generation: ‘-malign-call’ Does nothing. Preserved for backward compatibility. ‘-mauto-modify-reg’ Enable the use of pre/post modify with register displacement. ‘-mbbit-peephole’ Does nothing. Preserved for backward compatibility. ‘-mno-brcc’ This option disables a target-specific pass in ‘arc_reorg’ to generate compare-and-branch (‘brCC’) instructions. It has no effect on generation of these instructions driven by the combiner pass. ‘-mcase-vector-pcrel’ Use PC-relative switch case tables to enable case table shortening. This is the default for ‘-Os’. ‘-mcompact-casesi’ Enable compact ‘casesi’ pattern. This is the default for ‘-Os’, and only available for ARCv1 cores. This option is deprecated. ‘-mno-cond-exec’ Disable the ARCompact-specific pass to generate conditional execution instructions. Due to delay slot scheduling and interactions between operand numbers, literal sizes, instruction lengths, and the support for conditional execution, the target-independent pass to generate conditional execution is often lacking, so the ARC port has kept a special pass around that tries to find more conditional execution generation opportunities after register allocation, branch shortening, and delay slot scheduling have been done. This pass generally, but not always, improves performance and code size, at the cost of extra compilation time, which is why there is an option to switch it off. If you have a problem with call instructions exceeding their allowable offset range because they are conditionalized, you should consider using ‘-mmedium-calls’ instead. ‘-mearly-cbranchsi’ Enable pre-reload use of the ‘cbranchsi’ pattern. ‘-mexpand-adddi’ Expand ‘adddi3’ and ‘subdi3’ at RTL generation time into ‘add.f’, ‘adc’ etc. This option is deprecated. ‘-mindexed-loads’ Enable the use of indexed loads. This can be problematic because some optimizers then assume that indexed stores exist, which is not the case. ‘-mlra’ Enable Local Register Allocation. This is still experimental for ARC, so by default the compiler uses standard reload (i.e. ‘-mno-lra’). ‘-mlra-priority-none’ Don't indicate any priority for target registers. ‘-mlra-priority-compact’ Indicate target register priority for r0..r3 / r12..r15. ‘-mlra-priority-noncompact’ Reduce target register priority for r0..r3 / r12..r15. ‘-mmillicode’ When optimizing for size (using ‘-Os’), prologues and epilogues that have to save or restore a large number of registers are often shortened by using call to a special function in libgcc; this is referred to as a _millicode_ call. As these calls can pose performance issues, and/or cause linking issues when linking in a nonstandard way, this option is provided to turn on or off millicode call generation. ‘-mcode-density-frame’ This option enable the compiler to emit ‘enter’ and ‘leave’ instructions. These instructions are only valid for CPUs with code-density feature. ‘-mmixed-code’ Does nothing. Preserved for backward compatibility. ‘-mq-class’ Ths option is deprecated. Enable ‘q’ instruction alternatives. This is the default for ‘-Os’. ‘-mRcq’ Does nothing. Preserved for backward compatibility. ‘-mRcw’ Does nothing. Preserved for backward compatibility. ‘-msize-level=LEVEL’ Fine-tune size optimization with regards to instruction lengths and alignment. The recognized values for LEVEL are: ‘0’ No size optimization. This level is deprecated and treated like ‘1’. ‘1’ Short instructions are used opportunistically. ‘2’ In addition, alignment of loops and of code after barriers are dropped. ‘3’ In addition, optional data alignment is dropped, and the option ‘Os’ is enabled. This defaults to ‘3’ when ‘-Os’ is in effect. Otherwise, the behavior when this is not set is equivalent to level ‘1’. ‘-mtune=CPU’ Set instruction scheduling parameters for CPU, overriding any implied by ‘-mcpu=’. Supported values for CPU are ‘ARC600’ Tune for ARC600 CPU. ‘ARC601’ Tune for ARC601 CPU. ‘ARC700’ Tune for ARC700 CPU with standard multiplier block. ‘ARC700-xmac’ Tune for ARC700 CPU with XMAC block. ‘ARC725D’ Tune for ARC725D CPU. ‘ARC750D’ Tune for ARC750D CPU. ‘core3’ Tune for ARCv2 core3 type CPU. This option enable usage of ‘dbnz’ instruction. ‘release31a’ Tune for ARC4x release 3.10a. ‘-mmultcost=NUM’ Cost to assume for a multiply instruction, with ‘4’ being equal to a normal instruction. ‘-munalign-prob-threshold=PROBABILITY’ Does nothing. Preserved for backward compatibility. The following options are maintained for backward compatibility, but are now deprecated and will be removed in a future release: ‘-margonaut’ Obsolete FPX. ‘-mbig-endian’ ‘-EB’ Compile code for big-endian targets. Use of these options is now deprecated. Big-endian code is supported by configuring GCC to build ‘arceb-elf32’ and ‘arceb-linux-uclibc’ targets, for which big endian is the default. ‘-mlittle-endian’ ‘-EL’ Compile code for little-endian targets. Use of these options is now deprecated. Little-endian code is supported by configuring GCC to build ‘arc-elf32’ and ‘arc-linux-uclibc’ targets, for which little endian is the default. ‘-mbarrel_shifter’ Replaced by ‘-mbarrel-shifter’. ‘-mdpfp_compact’ Replaced by ‘-mdpfp-compact’. ‘-mdpfp_fast’ Replaced by ‘-mdpfp-fast’. ‘-mdsp_packa’ Replaced by ‘-mdsp-packa’. ‘-mEA’ Replaced by ‘-mea’. ‘-mmac_24’ Replaced by ‘-mmac-24’. ‘-mmac_d16’ Replaced by ‘-mmac-d16’. ‘-mspfp_compact’ Replaced by ‘-mspfp-compact’. ‘-mspfp_fast’ Replaced by ‘-mspfp-fast’. ‘-mtune=CPU’ Values ‘arc600’, ‘arc601’, ‘arc700’ and ‘arc700-xmac’ for CPU are replaced by ‘ARC600’, ‘ARC601’, ‘ARC700’ and ‘ARC700-xmac’ respectively. ‘-multcost=NUM’ Replaced by ‘-mmultcost’.  File: gcc.info, Node: ARM Options, Next: AVR Options, Prev: ARC Options, Up: Submodel Options 3.19.5 ARM Options ------------------ These ‘-m’ options are defined for the ARM port: ‘-mabi=NAME’ Generate code for the specified ABI. Permissible values are: ‘apcs-gnu’, ‘atpcs’, ‘aapcs’, ‘aapcs-linux’ and ‘iwmmxt’. ‘-mapcs-frame’ Generate a stack frame that is compliant with the ARM Procedure Call Standard for all functions, even if this is not strictly necessary for correct execution of the code. Specifying ‘-fomit-frame-pointer’ with this option causes the stack frames not to be generated for leaf functions. The default is ‘-mno-apcs-frame’. This option is deprecated. ‘-mapcs’ This is a synonym for ‘-mapcs-frame’ and is deprecated. ‘-mthumb-interwork’ Generate code that supports calling between the ARM and Thumb instruction sets. Without this option, on pre-v5 architectures, the two instruction sets cannot be reliably used inside one program. The default is ‘-mno-thumb-interwork’, since slightly larger code is generated when ‘-mthumb-interwork’ is specified. In AAPCS configurations this option is meaningless. ‘-mno-sched-prolog’ Prevent the reordering of instructions in the function prologue, or the merging of those instruction with the instructions in the function's body. This means that all functions start with a recognizable set of instructions (or in fact one of a choice from a small set of different function prologues), and this information can be used to locate the start of functions inside an executable piece of code. The default is ‘-msched-prolog’. ‘-mfloat-abi=NAME’ Specifies which floating-point ABI to use. Permissible values are: ‘soft’, ‘softfp’ and ‘hard’. Specifying ‘soft’ causes GCC to generate output containing library calls for floating-point operations. ‘softfp’ allows the generation of code using hardware floating-point instructions, but still uses the soft-float calling conventions. ‘hard’ allows generation of floating-point instructions and uses FPU-specific calling conventions. The default depends on the specific target configuration. Note that the hard-float and soft-float ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries. ‘-mgeneral-regs-only’ Generate code which uses only the general-purpose registers. This will prevent the compiler from using floating-point and Advanced SIMD registers but will not impose any restrictions on the assembler. ‘-mlittle-endian’ Generate code for a processor running in little-endian mode. This is the default for all standard configurations. ‘-mbig-endian’ Generate code for a processor running in big-endian mode; the default is to compile code for a little-endian processor. ‘-mbe8’ ‘-mbe32’ When linking a big-endian image select between BE8 and BE32 formats. The option has no effect for little-endian images and is ignored. The default is dependent on the selected target architecture. For ARMv6 and later architectures the default is BE8, for older architectures the default is BE32. BE32 format has been deprecated by ARM. ‘-march=NAME[+extension...]’ This specifies the name of the target ARM architecture. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. This option can be used in conjunction with or instead of the ‘-mcpu=’ option. Permissible names are: ‘armv4t’, ‘armv5t’, ‘armv5te’, ‘armv6’, ‘armv6j’, ‘armv6k’, ‘armv6kz’, ‘armv6t2’, ‘armv6z’, ‘armv6zk’, ‘armv7’, ‘armv7-a’, ‘armv7ve’, ‘armv8-a’, ‘armv8.1-a’, ‘armv8.2-a’, ‘armv8.3-a’, ‘armv8.4-a’, ‘armv8.5-a’, ‘armv8.6-a’, ‘armv9-a’, ‘armv7-r’, ‘armv8-r’, ‘armv6-m’, ‘armv6s-m’, ‘armv7-m’, ‘armv7e-m’, ‘armv8-m.base’, ‘armv8-m.main’, ‘armv8.1-m.main’, ‘armv9-a’, ‘iwmmxt’ and ‘iwmmxt2’. Additionally, the following architectures, which lack support for the Thumb execution state, are recognized but support is deprecated: ‘armv4’. Many of the architectures support extensions. These can be added by appending ‘+EXTENSION’ to the architecture name. Extension options are processed in order and capabilities accumulate. An extension will also enable any necessary base extensions upon which it depends. For example, the ‘+crypto’ extension will always enable the ‘+simd’ extension. The exception to the additive construction is for extensions that are prefixed with ‘+no...’: these extensions disable the specified option and any other extensions that may depend on the presence of that extension. For example, ‘-march=armv7-a+simd+nofp+vfpv4’ is equivalent to writing ‘-march=armv7-a+vfpv4’ since the ‘+simd’ option is entirely disabled by the ‘+nofp’ option that follows it. Most extension names are generically named, but have an effect that is dependent upon the architecture to which it is applied. For example, the ‘+simd’ option can be applied to both ‘armv7-a’ and ‘armv8-a’ architectures, but will enable the original ARMv7-A Advanced SIMD (Neon) extensions for ‘armv7-a’ and the ARMv8-A variant for ‘armv8-a’. The table below lists the supported extensions for each architecture. Architectures not mentioned do not support any extensions. ‘armv5te’ ‘armv6’ ‘armv6j’ ‘armv6k’ ‘armv6kz’ ‘armv6t2’ ‘armv6z’ ‘armv6zk’ ‘+fp’ The VFPv2 floating-point instructions. The extension ‘+vfpv2’ can be used as an alias for this extension. ‘+nofp’ Disable the floating-point instructions. ‘armv7’ The common subset of the ARMv7-A, ARMv7-R and ARMv7-M architectures. ‘+fp’ The VFPv3 floating-point instructions, with 16 double-precision registers. The extension ‘+vfpv3-d16’ can be used as an alias for this extension. Note that floating-point is not supported by the base ARMv7-M architecture, but is compatible with both the ARMv7-A and ARMv7-R architectures. ‘+nofp’ Disable the floating-point instructions. ‘armv7-a’ ‘+mp’ The multiprocessing extension. ‘+sec’ The security extension. ‘+fp’ The VFPv3 floating-point instructions, with 16 double-precision registers. The extension ‘+vfpv3-d16’ can be used as an alias for this extension. ‘+simd’ The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. The extensions ‘+neon’ and ‘+neon-vfpv3’ can be used as aliases for this extension. ‘+vfpv3’ The VFPv3 floating-point instructions, with 32 double-precision registers. ‘+vfpv3-d16-fp16’ The VFPv3 floating-point instructions, with 16 double-precision registers and the half-precision floating-point conversion operations. ‘+vfpv3-fp16’ The VFPv3 floating-point instructions, with 32 double-precision registers and the half-precision floating-point conversion operations. ‘+vfpv4-d16’ The VFPv4 floating-point instructions, with 16 double-precision registers. ‘+vfpv4’ The VFPv4 floating-point instructions, with 32 double-precision registers. ‘+neon-fp16’ The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with the half-precision floating-point conversion operations. ‘+neon-vfpv4’ The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions. ‘+nosimd’ Disable the Advanced SIMD instructions (does not disable floating point). ‘+nofp’ Disable the floating-point and Advanced SIMD instructions. ‘armv7ve’ The extended version of the ARMv7-A architecture with support for virtualization. ‘+fp’ The VFPv4 floating-point instructions, with 16 double-precision registers. The extension ‘+vfpv4-d16’ can be used as an alias for this extension. ‘+simd’ The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions. The extension ‘+neon-vfpv4’ can be used as an alias for this extension. ‘+vfpv3-d16’ The VFPv3 floating-point instructions, with 16 double-precision registers. ‘+vfpv3’ The VFPv3 floating-point instructions, with 32 double-precision registers. ‘+vfpv3-d16-fp16’ The VFPv3 floating-point instructions, with 16 double-precision registers and the half-precision floating-point conversion operations. ‘+vfpv3-fp16’ The VFPv3 floating-point instructions, with 32 double-precision registers and the half-precision floating-point conversion operations. ‘+vfpv4-d16’ The VFPv4 floating-point instructions, with 16 double-precision registers. ‘+vfpv4’ The VFPv4 floating-point instructions, with 32 double-precision registers. ‘+neon’ The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. The extension ‘+neon-vfpv3’ can be used as an alias for this extension. ‘+neon-fp16’ The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with the half-precision floating-point conversion operations. ‘+nosimd’ Disable the Advanced SIMD instructions (does not disable floating point). ‘+nofp’ Disable the floating-point and Advanced SIMD instructions. ‘armv8-a’ ‘+crc’ The Cyclic Redundancy Check (CRC) instructions. ‘+simd’ The ARMv8-A Advanced SIMD and floating-point instructions. ‘+crypto’ The cryptographic instructions. ‘+nocrypto’ Disable the cryptographic instructions. ‘+nofp’ Disable the floating-point, Advanced SIMD and cryptographic instructions. ‘+sb’ Speculation Barrier Instruction. ‘+predres’ Execution and Data Prediction Restriction Instructions. ‘armv8.1-a’ ‘+simd’ The ARMv8.1-A Advanced SIMD and floating-point instructions. ‘+crypto’ The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions. ‘+nocrypto’ Disable the cryptographic instructions. ‘+nofp’ Disable the floating-point, Advanced SIMD and cryptographic instructions. ‘+sb’ Speculation Barrier Instruction. ‘+predres’ Execution and Data Prediction Restriction Instructions. ‘armv8.2-a’ ‘armv8.3-a’ ‘+fp16’ The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions. ‘+fp16fml’ The half-precision floating-point fmla extension. This also enables the half-precision floating-point extension and Advanced SIMD and floating-point instructions. ‘+simd’ The ARMv8.1-A Advanced SIMD and floating-point instructions. ‘+crypto’ The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions. ‘+dotprod’ Enable the Dot Product extension. This also enables Advanced SIMD instructions. ‘+nocrypto’ Disable the cryptographic extension. ‘+nofp’ Disable the floating-point, Advanced SIMD and cryptographic instructions. ‘+sb’ Speculation Barrier Instruction. ‘+predres’ Execution and Data Prediction Restriction Instructions. ‘+i8mm’ 8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions. ‘+bf16’ Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions. ‘armv8.4-a’ ‘+fp16’ The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension and the half-precision floating-point fmla extension. ‘+simd’ The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension. ‘+crypto’ The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension. ‘+nocrypto’ Disable the cryptographic extension. ‘+nofp’ Disable the floating-point, Advanced SIMD and cryptographic instructions. ‘+sb’ Speculation Barrier Instruction. ‘+predres’ Execution and Data Prediction Restriction Instructions. ‘+i8mm’ 8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions. ‘+bf16’ Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions. ‘armv8.5-a’ ‘+fp16’ The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension and the half-precision floating-point fmla extension. ‘+simd’ The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension. ‘+crypto’ The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension. ‘+nocrypto’ Disable the cryptographic extension. ‘+nofp’ Disable the floating-point, Advanced SIMD and cryptographic instructions. ‘+i8mm’ 8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions. ‘+bf16’ Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions. ‘armv8.6-a’ ‘+fp16’ The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension and the half-precision floating-point fmla extension. ‘+simd’ The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension. ‘+crypto’ The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension. ‘+nocrypto’ Disable the cryptographic extension. ‘+nofp’ Disable the floating-point, Advanced SIMD and cryptographic instructions. ‘+i8mm’ 8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions. ‘+bf16’ Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions. ‘armv7-r’ ‘+fp.sp’ The single-precision VFPv3 floating-point instructions. The extension ‘+vfpv3xd’ can be used as an alias for this extension. ‘+fp’ The VFPv3 floating-point instructions with 16 double-precision registers. The extension +vfpv3-d16 can be used as an alias for this extension. ‘+vfpv3xd-d16-fp16’ The single-precision VFPv3 floating-point instructions with 16 double-precision registers and the half-precision floating-point conversion operations. ‘+vfpv3-d16-fp16’ The VFPv3 floating-point instructions with 16 double-precision registers and the half-precision floating-point conversion operations. ‘+nofp’ Disable the floating-point extension. ‘+idiv’ The ARM-state integer division instructions. ‘+noidiv’ Disable the ARM-state integer division extension. ‘armv7e-m’ ‘+fp’ The single-precision VFPv4 floating-point instructions. ‘+fpv5’ The single-precision FPv5 floating-point instructions. ‘+fp.dp’ The single- and double-precision FPv5 floating-point instructions. ‘+nofp’ Disable the floating-point extensions. ‘armv8.1-m.main’ ‘+dsp’ The DSP instructions. ‘+mve’ The M-Profile Vector Extension (MVE) integer instructions. ‘+mve.fp’ The M-Profile Vector Extension (MVE) integer and single precision floating-point instructions. ‘+fp’ The single-precision floating-point instructions. ‘+fp.dp’ The single- and double-precision floating-point instructions. ‘+nofp’ Disable the floating-point extension. ‘+cdecp0, +cdecp1, ... , +cdecp7’ Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given in the options in the range 0 to 7. ‘+pacbti’ Enable the Pointer Authentication and Branch Target Identification Extension. ‘armv8-m.main’ ‘+dsp’ The DSP instructions. ‘+nodsp’ Disable the DSP extension. ‘+fp’ The single-precision floating-point instructions. ‘+fp.dp’ The single- and double-precision floating-point instructions. ‘+nofp’ Disable the floating-point extension. ‘+cdecp0, +cdecp1, ... , +cdecp7’ Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given in the options in the range 0 to 7. ‘armv8-r’ ‘+crc’ The Cyclic Redundancy Check (CRC) instructions. ‘+fp.sp’ The single-precision FPv5 floating-point instructions. ‘+simd’ The ARMv8-A Advanced SIMD and floating-point instructions. ‘+crypto’ The cryptographic instructions. ‘+nocrypto’ Disable the cryptographic instructions. ‘+nofp’ Disable the floating-point, Advanced SIMD and cryptographic instructions. ‘-march=native’ causes the compiler to auto-detect the architecture of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. ‘-mtune=NAME’ This option specifies the name of the target ARM processor for which GCC should tune the performance of the code. For some ARM implementations better performance can be obtained by using this option. Permissible names are: ‘arm7tdmi’, ‘arm7tdmi-s’, ‘arm710t’, ‘arm720t’, ‘arm740t’, ‘strongarm’, ‘strongarm110’, ‘strongarm1100’, ‘strongarm1110’, ‘arm8’, ‘arm810’, ‘arm9’, ‘arm9e’, ‘arm920’, ‘arm920t’, ‘arm922t’, ‘arm946e-s’, ‘arm966e-s’, ‘arm968e-s’, ‘arm926ej-s’, ‘arm940t’, ‘arm9tdmi’, ‘arm10tdmi’, ‘arm1020t’, ‘arm1026ej-s’, ‘arm10e’, ‘arm1020e’, ‘arm1022e’, ‘arm1136j-s’, ‘arm1136jf-s’, ‘mpcore’, ‘mpcorenovfp’, ‘arm1156t2-s’, ‘arm1156t2f-s’, ‘arm1176jz-s’, ‘arm1176jzf-s’, ‘generic-armv7-a’, ‘cortex-a5’, ‘cortex-a7’, ‘cortex-a8’, ‘cortex-a9’, ‘cortex-a12’, ‘cortex-a15’, ‘cortex-a17’, ‘cortex-a32’, ‘cortex-a35’, ‘cortex-a53’, ‘cortex-a55’, ‘cortex-a57’, ‘cortex-a72’, ‘cortex-a73’, ‘cortex-a75’, ‘cortex-a76’, ‘cortex-a76ae’, ‘cortex-a77’, ‘cortex-a78’, ‘cortex-a78ae’, ‘cortex-a78c’, ‘cortex-a710’, ‘ares’, ‘cortex-r4’, ‘cortex-r4f’, ‘cortex-r5’, ‘cortex-r7’, ‘cortex-r8’, ‘cortex-r52’, ‘cortex-r52plus’, ‘cortex-m0’, ‘cortex-m0plus’, ‘cortex-m1’, ‘cortex-m3’, ‘cortex-m4’, ‘cortex-m7’, ‘cortex-m23’, ‘cortex-m33’, ‘cortex-m35p’, ‘cortex-m52’, ‘cortex-m55’, ‘cortex-m85’, ‘cortex-x1’, ‘cortex-x1c’, ‘cortex-m1.small-multiply’, ‘cortex-m0.small-multiply’, ‘cortex-m0plus.small-multiply’, ‘exynos-m1’, ‘marvell-pj4’, ‘neoverse-n1’, ‘neoverse-n2’, ‘neoverse-v1’, ‘xscale’, ‘iwmmxt’, ‘iwmmxt2’, ‘ep9312’, ‘fa526’, ‘fa626’, ‘fa606te’, ‘fa626te’, ‘fmp626’, ‘fa726te’, ‘star-mc1’, ‘xgene1’. Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: ‘cortex-a15.cortex-a7’, ‘cortex-a17.cortex-a7’, ‘cortex-a57.cortex-a53’, ‘cortex-a72.cortex-a53’, ‘cortex-a72.cortex-a35’, ‘cortex-a73.cortex-a53’, ‘cortex-a75.cortex-a55’, ‘cortex-a76.cortex-a55’. ‘-mtune=generic-ARCH’ specifies that GCC should tune the performance for a blend of processors within architecture ARCH. The aim is to generate code that run well on the current most popular processors, balancing between optimizations that benefit some CPUs in the range, and avoiding performance pitfalls of other CPUs. The effects of this option may change in future GCC versions as CPU models come and go. ‘-mtune’ permits the same extension options as ‘-mcpu’, but the extension options do not affect the tuning of the generated code. ‘-mtune=native’ causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. ‘-mcpu=NAME[+extension...]’ This specifies the name of the target ARM processor. GCC uses this name to derive the name of the target ARM architecture (as if specified by ‘-march’) and the ARM processor type for which to tune for performance (as if specified by ‘-mtune’). Where this option is used in conjunction with ‘-march’ or ‘-mtune’, those options take precedence over the appropriate part of this option. Many of the supported CPUs implement optional architectural extensions. Where this is so the architectural extensions are normally enabled by default. If implementations that lack the extension exist, then the extension syntax can be used to disable those extensions that have been omitted. For floating-point and Advanced SIMD (Neon) instructions, the settings of the options ‘-mfloat-abi’ and ‘-mfpu’ must also be considered: floating-point and Advanced SIMD instructions will only be used if ‘-mfloat-abi’ is not set to ‘soft’; and any setting of ‘-mfpu’ other than ‘auto’ will override the available floating-point and SIMD extension instructions. For example, ‘cortex-a9’ can be found in three major configurations: integer only, with just a floating-point unit or with floating-point and Advanced SIMD. The default is to enable all the instructions, but the extensions ‘+nosimd’ and ‘+nofp’ can be used to disable just the SIMD or both the SIMD and floating-point instructions respectively. Permissible names for this option are the same as those for ‘-mtune’. The following extension options are common to the listed CPUs: ‘+nodsp’ Disable the DSP instructions on ‘cortex-m33’, ‘cortex-m35p’, ‘cortex-m52’, ‘cortex-m55’ and ‘cortex-m85’. Also disable the M-Profile Vector Extension (MVE) integer and single precision floating-point instructions on ‘cortex-m52’, ‘cortex-m55’ and ‘cortex-m85’. ‘+nopacbti’ Disable the Pointer Authentication and Branch Target Identification Extension on ‘cortex-m52’ and ‘cortex-m85’. ‘+nomve’ Disable the M-Profile Vector Extension (MVE) integer and single precision floating-point instructions on ‘cortex-m52’, ‘cortex-m55’ and ‘cortex-m85’. ‘+nomve.fp’ Disable the M-Profile Vector Extension (MVE) single precision floating-point instructions on ‘cortex-m52’, ‘cortex-m55’ and ‘cortex-m85’. ‘+cdecp0, +cdecp1, ... , +cdecp7’ Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given in the options in the range 0 to 7 on ‘cortex-m52’ and ‘cortex-m55’. ‘+nofp’ Disables the floating-point instructions on ‘arm9e’, ‘arm946e-s’, ‘arm966e-s’, ‘arm968e-s’, ‘arm10e’, ‘arm1020e’, ‘arm1022e’, ‘arm926ej-s’, ‘arm1026ej-s’, ‘cortex-r5’, ‘cortex-r7’, ‘cortex-r8’, ‘cortex-m4’, ‘cortex-m7’, ‘cortex-m33’, ‘cortex-m35p’, ‘cortex-m52’, ‘cortex-m55’ and ‘cortex-m85’. Disables the floating-point and SIMD instructions on ‘generic-armv7-a’, ‘cortex-a5’, ‘cortex-a7’, ‘cortex-a8’, ‘cortex-a9’, ‘cortex-a12’, ‘cortex-a15’, ‘cortex-a17’, ‘cortex-a15.cortex-a7’, ‘cortex-a17.cortex-a7’, ‘cortex-a32’, ‘cortex-a35’, ‘cortex-a53’ and ‘cortex-a55’. ‘+nofp.dp’ Disables the double-precision component of the floating-point instructions on ‘cortex-r5’, ‘cortex-r7’, ‘cortex-r8’, ‘cortex-r52’, ‘cortex-r52plus’ and ‘cortex-m7’. ‘+nosimd’ Disables the SIMD (but not floating-point) instructions on ‘generic-armv7-a’, ‘cortex-a5’, ‘cortex-a7’ and ‘cortex-a9’. ‘+crypto’ Enables the cryptographic instructions on ‘cortex-a32’, ‘cortex-a35’, ‘cortex-a53’, ‘cortex-a55’, ‘cortex-a57’, ‘cortex-a72’, ‘cortex-a73’, ‘cortex-a75’, ‘exynos-m1’, ‘xgene1’, ‘cortex-a57.cortex-a53’, ‘cortex-a72.cortex-a53’, ‘cortex-a73.cortex-a35’, ‘cortex-a73.cortex-a53’ and ‘cortex-a75.cortex-a55’. Additionally the ‘generic-armv7-a’ pseudo target defaults to VFPv3 with 16 double-precision registers. It supports the following extension options: ‘mp’, ‘sec’, ‘vfpv3-d16’, ‘vfpv3’, ‘vfpv3-d16-fp16’, ‘vfpv3-fp16’, ‘vfpv4-d16’, ‘vfpv4’, ‘neon’, ‘neon-vfpv3’, ‘neon-fp16’, ‘neon-vfpv4’. The meanings are the same as for the extensions to ‘-march=armv7-a’. ‘-mcpu=generic-ARCH’ is also permissible, and is equivalent to ‘-march=ARCH -mtune=generic-ARCH’. See ‘-mtune’ for more information. ‘-mcpu=native’ causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. ‘-mfpu=NAME’ This specifies what floating-point hardware (or hardware emulation) is available on the target. Permissible names are: ‘auto’, ‘vfpv2’, ‘vfpv3’, ‘vfpv3-fp16’, ‘vfpv3-d16’, ‘vfpv3-d16-fp16’, ‘vfpv3xd’, ‘vfpv3xd-fp16’, ‘neon-vfpv3’, ‘neon-fp16’, ‘vfpv4’, ‘vfpv4-d16’, ‘fpv4-sp-d16’, ‘neon-vfpv4’, ‘fpv5-d16’, ‘fpv5-sp-d16’, ‘fp-armv8’, ‘neon-fp-armv8’ and ‘crypto-neon-fp-armv8’. Note that ‘neon’ is an alias for ‘neon-vfpv3’ and ‘vfp’ is an alias for ‘vfpv2’. The setting ‘auto’ is the default and is special. It causes the compiler to select the floating-point and Advanced SIMD instructions based on the settings of ‘-mcpu’ and ‘-march’. If the selected floating-point hardware includes the NEON extension (e.g. ‘-mfpu=neon’), note that floating-point operations are not generated by GCC's auto-vectorization pass unless ‘-funsafe-math-optimizations’ is also specified. This is because NEON hardware does not fully implement the IEEE 754 standard for floating-point arithmetic (in particular denormal values are treated as zero), so the use of NEON instructions may lead to a loss of precision. You can also set the fpu name at function level by using the ‘target("fpu=")’ function attributes (*note ARM Function Attributes::) or pragmas (*note Function Specific Option Pragmas::). ‘-mfp16-format=NAME’ Specify the format of the ‘__fp16’ half-precision floating-point type. Permissible names are ‘none’, ‘ieee’, and ‘alternative’; the default is ‘none’, in which case the ‘__fp16’ type is not defined. *Note Half-Precision::, for more information. ‘-mstructure-size-boundary=N’ The sizes of all structures and unions are rounded up to a multiple of the number of bits set by this option. Permissible values are 8, 32 and 64. The default value varies for different toolchains. For the COFF targeted toolchain the default value is 8. A value of 64 is only allowed if the underlying ABI supports it. Specifying a larger number can produce faster, more efficient code, but can also increase the size of the program. Different values are potentially incompatible. Code compiled with one value cannot necessarily expect to work with code or libraries compiled with another value, if they exchange information using structures or unions. This option is deprecated. ‘-mabort-on-noreturn’ Generate a call to the function ‘abort’ at the end of a ‘noreturn’ function. It is executed if the function tries to return. ‘-mlong-calls’ ‘-mno-long-calls’ Tells the compiler to perform function calls by first loading the address of the function into a register and then performing a subroutine call on this register. This switch is needed if the target function lies outside of the 64-megabyte addressing range of the offset-based version of subroutine call instruction. Even if this switch is enabled, not all function calls are turned into long calls. The heuristic is that static functions, functions that have the ‘short_call’ attribute, functions that are inside the scope of a ‘#pragma no_long_calls’ directive, and functions whose definitions have already been compiled within the current compilation unit are not turned into long calls. The exceptions to this rule are that weak function definitions, functions with the ‘long_call’ attribute or the ‘section’ attribute, and functions that are within the scope of a ‘#pragma long_calls’ directive are always turned into long calls. This feature is not enabled by default. Specifying ‘-mno-long-calls’ restores the default behavior, as does placing the function calls within the scope of a ‘#pragma long_calls_off’ directive. Note these switches have no effect on how the compiler generates code to handle function calls via function pointers. ‘-msingle-pic-base’ Treat the register used for PIC addressing as read-only, rather than loading it in the prologue for each function. The runtime system is responsible for initializing this register with an appropriate value before execution begins. ‘-mpic-register=REG’ Specify the register to be used for PIC addressing. For standard PIC base case, the default is any suitable register determined by compiler. For single PIC base case, the default is ‘R9’ if target is EABI based or stack-checking is enabled, otherwise the default is ‘R10’. ‘-mpic-data-is-text-relative’ Assume that the displacement between the text and data segments is fixed at static link time. This permits using PC-relative addressing operations to access data known to be in the data segment. For non-VxWorks RTP targets, this option is enabled by default. When disabled on such targets, it will enable ‘-msingle-pic-base’ by default. ‘-mpoke-function-name’ Write the name of each function into the text section, directly preceding the function prologue. The generated code is similar to this: t0 .ascii "arm_poke_function_name", 0 .align t1 .word 0xff000000 + (t1 - t0) arm_poke_function_name mov ip, sp stmfd sp!, {fp, ip, lr, pc} sub fp, ip, #4 When performing a stack backtrace, code can inspect the value of ‘pc’ stored at ‘fp + 0’. If the trace function then looks at location ‘pc - 12’ and the top 8 bits are set, then we know that there is a function name embedded immediately preceding this location and has length ‘((pc[-3]) & 0xff000000)’. ‘-mthumb’ ‘-marm’ Select between generating code that executes in ARM and Thumb states. The default for most configurations is to generate code that executes in ARM state, but the default can be changed by configuring GCC with the ‘--with-mode=’STATE configure option. You can also override the ARM and Thumb mode for each function by using the ‘target("thumb")’ and ‘target("arm")’ function attributes (*note ARM Function Attributes::) or pragmas (*note Function Specific Option Pragmas::). ‘-mflip-thumb’ Switch ARM/Thumb modes on alternating functions. This option is provided for regression testing of mixed Thumb/ARM code generation, and is not intended for ordinary use in compiling code. ‘-mtpcs-frame’ Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all non-leaf functions. (A leaf function is one that does not call any other functions.) The default is ‘-mno-tpcs-frame’. ‘-mtpcs-leaf-frame’ Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all leaf functions. (A leaf function is one that does not call any other functions.) The default is ‘-mno-apcs-leaf-frame’. ‘-mcallee-super-interworking’ Gives all externally visible functions in the file being compiled an ARM instruction set header which switches to Thumb mode before executing the rest of the function. This allows these functions to be called from non-interworking code. This option is not valid in AAPCS configurations because interworking is enabled by default. ‘-mcaller-super-interworking’ Allows calls via function pointers (including virtual functions) to execute correctly regardless of whether the target code has been compiled for interworking or not. There is a small overhead in the cost of executing a function pointer if this option is enabled. This option is not valid in AAPCS configurations because interworking is enabled by default. ‘-mtp=NAME’ Specify the access model for the thread local storage pointer. The model ‘soft’ generates calls to ‘__aeabi_read_tp’. Other accepted models are ‘tpidrurw’, ‘tpidruro’ and ‘tpidrprw’ which fetch the thread pointer from the corresponding system register directly (supported from the arm6k architecture and later). These system registers are accessed through the CP15 co-processor interface and the argument ‘cp15’ is also accepted as a convenience alias of ‘tpidruro’. The argument ‘auto’ uses the best available method for the selected processor. The default setting is ‘auto’. ‘-mtls-dialect=DIALECT’ Specify the dialect to use for accessing thread local storage. Two DIALECTs are supported--‘gnu’ and ‘gnu2’. The ‘gnu’ dialect selects the original GNU scheme for supporting local and global dynamic TLS models. The ‘gnu2’ dialect selects the GNU descriptor scheme, which provides better performance for shared libraries. The GNU descriptor scheme is compatible with the original scheme, but does require new assembler, linker and library support. Initial and local exec TLS models are unaffected by this option and always use the original scheme. ‘-mword-relocations’ Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32). This is enabled by default on targets (uClinux, SymbianOS) where the runtime loader imposes this restriction, and when ‘-fpic’ or ‘-fPIC’ is specified. This option conflicts with ‘-mslow-flash-data’. ‘-mfix-cortex-m3-ldrd’ Some Cortex-M3 cores can cause data corruption when ‘ldrd’ instructions with overlapping destination and base registers are used. This option avoids generating these instructions. This option is enabled by default when ‘-mcpu=cortex-m3’ is specified. ‘-mfix-cortex-a57-aes-1742098’ ‘-mno-fix-cortex-a57-aes-1742098’ ‘-mfix-cortex-a72-aes-1655431’ ‘-mno-fix-cortex-a72-aes-1655431’ Enable (disable) mitigation for an erratum on Cortex-A57 and Cortex-A72 that affects the AES cryptographic instructions. This option is enabled by default when either ‘-mcpu=cortex-a57’ or ‘-mcpu=cortex-a72’ is specified. ‘-munaligned-access’ ‘-mno-unaligned-access’ Enables (or disables) reading and writing of 16- and 32- bit values from addresses that are not 16- or 32- bit aligned. By default unaligned access is disabled for all pre-ARMv6, all ARMv6-M and for ARMv8-M Baseline architectures, and enabled for all other architectures. If unaligned access is not enabled then words in packed data structures are accessed a byte at a time. The ARM attribute ‘Tag_CPU_unaligned_access’ is set in the generated object file to either true or false, depending upon the setting of this option. If unaligned access is enabled then the preprocessor symbol ‘__ARM_FEATURE_UNALIGNED’ is also defined. ‘-mneon-for-64bits’ This option is deprecated and has no effect. ‘-mslow-flash-data’ Assume loading data from flash is slower than fetching instruction. Therefore literal load is minimized for better performance. This option is only supported when compiling for ARMv7 M-profile and off by default. It conflicts with ‘-mword-relocations’. ‘-masm-syntax-unified’ Assume inline assembler is using unified asm syntax. The default is currently off which implies divided syntax. This option has no impact on Thumb2. However, this may change in future releases of GCC. Divided syntax should be considered deprecated. ‘-mrestrict-it’ Restricts generation of IT blocks to conform to the rules of ARMv8-A. IT blocks can only contain a single 16-bit instruction from a select set of instructions. This option is on by default for ARMv8-A Thumb mode. ‘-mprint-tune-info’ Print CPU tuning information as comment in assembler file. This is an option used only for regression testing of the compiler and not intended for ordinary use in compiling code. This option is disabled by default. ‘-mverbose-cost-dump’ Enable verbose cost model dumping in the debug dump files. This option is provided for use in debugging the compiler. ‘-mpure-code’ Do not allow constant data to be placed in code sections. Additionally, when compiling for ELF object format give all text sections the ELF processor-specific section attribute ‘SHF_ARM_PURECODE’. This option is only available when generating non-pic code for M-profile targets. ‘-mcmse’ Generate secure code as per the "ARMv8-M Security Extensions: Requirements on Development Tools Engineering Specification", which can be found on . ‘-mfix-cmse-cve-2021-35465’ Mitigate against a potential security issue with the ‘VLLDM’ instruction in some M-profile devices when using CMSE (CVE-2021-365465). This option is enabled by default when the option ‘-mcpu=’ is used with ‘cortex-m33’, ‘cortex-m35p’, ‘cortex-m52’, ‘cortex-m55’, ‘cortex-m85’ or ‘star-mc1’. The option ‘-mno-fix-cmse-cve-2021-35465’ can be used to disable the mitigation. ‘-mstack-protector-guard=GUARD’ ‘-mstack-protector-guard-offset=OFFSET’ Generate stack protection code using canary at GUARD. Supported locations are ‘global’ for a global canary or ‘tls’ for a canary accessible via the TLS register. The option ‘-mstack-protector-guard-offset=’ is for use with ‘-fstack-protector-guard=tls’ and not for use in user-land code. ‘-mfdpic’ ‘-mno-fdpic’ Select the FDPIC ABI, which uses 64-bit function descriptors to represent pointers to functions. When the compiler is configured for ‘arm-*-uclinuxfdpiceabi’ targets, this option is on by default and implies ‘-fPIE’ if none of the PIC/PIE-related options is provided. On other targets, it only enables the FDPIC-specific code generation features, and the user should explicitly provide the PIC/PIE-related options as needed. Note that static linking is not supported because it would still involve the dynamic linker when the program self-relocates. If such behavior is acceptable, use -static and -Wl,-dynamic-linker options. The opposite ‘-mno-fdpic’ option is useful (and required) to build the Linux kernel using the same (‘arm-*-uclinuxfdpiceabi’) toolchain as the one used to build the userland programs. ‘-mbranch-protection=NONE|STANDARD|PAC-RET[+LEAF][+BTI]|BTI[+PAC-RET[+LEAF]]’ Enable branch protection features (armv8.1-m.main only). ‘none’ generate code without branch protection or return address signing. ‘standard[+LEAF]’ generate code with all branch protection features enabled at their standard level. ‘pac-ret[+LEAF]’ generate code with return address signing set to its standard level, which is to sign all functions that save the return address to memory. ‘leaf’ When return address signing is enabled, also sign leaf functions even if they do not write the return address to memory. +‘bti’ Add landing-pad instructions at the permitted targets of indirect branch instructions. If the ‘+pacbti’ architecture extension is not enabled, then all branch protection and return address signing operations are constrained to use only the instructions defined in the architectural-NOP space. The generated code will remain backwards-compatible with earlier versions of the architecture, but the additional security can be enabled at run time on processors that support the ‘PACBTI’ extension. Branch target enforcement using BTI can only be enabled at runtime if all code in the application has been compiled with at least ‘-mbranch-protection=bti’. Any setting other than ‘none’ is supported only on armv8-m.main or later. The default is to generate code without branch protection or return address signing.  File: gcc.info, Node: AVR Options, Next: Blackfin Options, Prev: ARM Options, Up: Submodel Options 3.19.6 AVR Options ------------------ These options are defined for AVR implementations: ‘-mmcu=MCU’ Specify the AVR instruction set architecture (ISA) or device type. The default for this option is ‘avr2’. The following AVR devices and ISAs are supported. _Note:_ A complete device support consists of startup code ‘crtMCU.o’, a device header ‘avr/io*.h’, a device library ‘libMCU.a’ and a device-specs (https://gcc.gnu.org/wiki/avr-gcc#spec-files) file ‘specs-MCU’. Only the latter is provided by the compiler according the supported ‘MCU’s below. The rest is supported by AVR-LibC (https://www.nongnu.org/avr-libc/), or by means of ‘atpack’ (https://gcc.gnu.org/wiki/avr-gcc#atpack) files from the hardware manufacturer. ‘avr2’ "Classic" devices with up to 8 KiB of program memory. MCU = ‘attiny22’, ‘attiny26’, ‘at90s2313’, ‘at90s2323’, ‘at90s2333’, ‘at90s2343’, ‘at90s4414’, ‘at90s4433’, ‘at90s4434’, ‘at90c8534’, ‘at90s8515’, ‘at90s8535’. ‘avr25’ "Classic" devices with up to 8 KiB of program memory and with the ‘MOVW’ instruction. MCU = ‘attiny13’, ‘attiny13a’, ‘attiny24’, ‘attiny24a’, ‘attiny25’, ‘attiny261’, ‘attiny261a’, ‘attiny2313’, ‘attiny2313a’, ‘attiny43u’, ‘attiny44’, ‘attiny44a’, ‘attiny45’, ‘attiny48’, ‘attiny441’, ‘attiny461’, ‘attiny461a’, ‘attiny4313’, ‘attiny84’, ‘attiny84a’, ‘attiny85’, ‘attiny87’, ‘attiny88’, ‘attiny828’, ‘attiny841’, ‘attiny861’, ‘attiny861a’, ‘ata5272’, ‘ata6616c’, ‘at86rf401’. ‘avr3’ "Classic" devices with 16 KiB up to 64 KiB of program memory. MCU = ‘at76c711’, ‘at43usb355’. ‘avr31’ "Classic" devices with 128 KiB of program memory. MCU = ‘atmega103’, ‘at43usb320’. ‘avr35’ "Classic" devices with 16 KiB up to 64 KiB of program memory and with the ‘MOVW’ instruction. MCU = ‘attiny167’, ‘attiny1634’, ‘atmega8u2’, ‘atmega16u2’, ‘atmega32u2’, ‘ata5505’, ‘ata6617c’, ‘ata664251’, ‘at90usb82’, ‘at90usb162’. ‘avr4’ "Enhanced" devices with up to 8 KiB of program memory. MCU = ‘atmega48’, ‘atmega48a’, ‘atmega48p’, ‘atmega48pa’, ‘atmega48pb’, ‘atmega8’, ‘atmega8a’, ‘atmega8hva’, ‘atmega88’, ‘atmega88a’, ‘atmega88p’, ‘atmega88pa’, ‘atmega88pb’, ‘atmega8515’, ‘atmega8535’, ‘ata5795’, ‘ata6285’, ‘ata6286’, ‘ata6289’, ‘ata6612c’, ‘at90pwm1’, ‘at90pwm2’, ‘at90pwm2b’, ‘at90pwm3’, ‘at90pwm3b’, ‘at90pwm81’. ‘avr5’ "Enhanced" devices with 16 KiB up to 64 KiB of program memory. MCU = ‘atmega16’, ‘atmega16a’, ‘atmega16hva’, ‘atmega16hva2’, ‘atmega16hvb’, ‘atmega16hvbrevb’, ‘atmega16m1’, ‘atmega16u4’, ‘atmega161’, ‘atmega162’, ‘atmega163’, ‘atmega164a’, ‘atmega164p’, ‘atmega164pa’, ‘atmega165’, ‘atmega165a’, ‘atmega165p’, ‘atmega165pa’, ‘atmega168’, ‘atmega168a’, ‘atmega168p’, ‘atmega168pa’, ‘atmega168pb’, ‘atmega169’, ‘atmega169a’, ‘atmega169p’, ‘atmega169pa’, ‘atmega32’, ‘atmega32a’, ‘atmega32c1’, ‘atmega32hvb’, ‘atmega32hvbrevb’, ‘atmega32m1’, ‘atmega32u4’, ‘atmega32u6’, ‘atmega323’, ‘atmega324a’, ‘atmega324p’, ‘atmega324pa’, ‘atmega324pb’, ‘atmega325’, ‘atmega325a’, ‘atmega325p’, ‘atmega325pa’, ‘atmega328’, ‘atmega328p’, ‘atmega328pb’, ‘atmega329’, ‘atmega329a’, ‘atmega329p’, ‘atmega329pa’, ‘atmega3250’, ‘atmega3250a’, ‘atmega3250p’, ‘atmega3250pa’, ‘atmega3290’, ‘atmega3290a’, ‘atmega3290p’, ‘atmega3290pa’, ‘atmega406’, ‘atmega64’, ‘atmega64a’, ‘atmega64c1’, ‘atmega64hve’, ‘atmega64hve2’, ‘atmega64m1’, ‘atmega64rfr2’, ‘atmega640’, ‘atmega644’, ‘atmega644a’, ‘atmega644p’, ‘atmega644pa’, ‘atmega644rfr2’, ‘atmega645’, ‘atmega645a’, ‘atmega645p’, ‘atmega649’, ‘atmega649a’, ‘atmega649p’, ‘atmega6450’, ‘atmega6450a’, ‘atmega6450p’, ‘atmega6490’, ‘atmega6490a’, ‘atmega6490p’, ‘ata5790’, ‘ata5790n’, ‘ata5791’, ‘ata6613c’, ‘ata6614q’, ‘ata5782’, ‘ata5831’, ‘ata8210’, ‘ata8510’, ‘ata5787’, ‘ata5835’, ‘ata5700m322’, ‘ata5702m322’, ‘at90pwm161’, ‘at90pwm216’, ‘at90pwm316’, ‘at90can32’, ‘at90can64’, ‘at90scr100’, ‘at90usb646’, ‘at90usb647’, ‘at94k’, ‘m3000’. ‘avr51’ "Enhanced" devices with 128 KiB of program memory. MCU = ‘atmega128’, ‘atmega128a’, ‘atmega128rfa1’, ‘atmega128rfr2’, ‘atmega1280’, ‘atmega1281’, ‘atmega1284’, ‘atmega1284p’, ‘atmega1284rfr2’, ‘at90can128’, ‘at90usb1286’, ‘at90usb1287’. ‘avr6’ "Enhanced" devices with 3-byte PC, i.e. with more than 128 KiB of program memory. MCU = ‘atmega256rfr2’, ‘atmega2560’, ‘atmega2561’, ‘atmega2564rfr2’. ‘avrxmega2’ "XMEGA" devices with more than 8 KiB and up to 64 KiB of program memory. MCU = ‘atxmega8e5’, ‘atxmega16a4’, ‘atxmega16a4u’, ‘atxmega16c4’, ‘atxmega16d4’, ‘atxmega16e5’, ‘atxmega32a4’, ‘atxmega32a4u’, ‘atxmega32c3’, ‘atxmega32c4’, ‘atxmega32d3’, ‘atxmega32d4’, ‘atxmega32e5’, ‘avr64da28’, ‘avr64da32’, ‘avr64da48’, ‘avr64da64’, ‘avr64db28’, ‘avr64db32’, ‘avr64db48’, ‘avr64db64’, ‘avr64dd14’, ‘avr64dd20’, ‘avr64dd28’, ‘avr64dd32’, ‘avr64du28’, ‘avr64du32’, ‘avr64ea28’, ‘avr64ea32’, ‘avr64ea48’. ‘avrxmega3’ "XMEGA" devices with up to 64 KiB of combined program memory and RAM, and with program memory visible in the RAM address space. MCU = ‘attiny202’, ‘attiny204’, ‘attiny212’, ‘attiny214’, ‘attiny402’, ‘attiny404’, ‘attiny406’, ‘attiny412’, ‘attiny414’, ‘attiny416’, ‘attiny416auto’, ‘attiny417’, ‘attiny424’, ‘attiny426’, ‘attiny427’, ‘attiny804’, ‘attiny806’, ‘attiny807’, ‘attiny814’, ‘attiny816’, ‘attiny817’, ‘attiny824’, ‘attiny826’, ‘attiny827’, ‘attiny1604’, ‘attiny1606’, ‘attiny1607’, ‘attiny1614’, ‘attiny1616’, ‘attiny1617’, ‘attiny1624’, ‘attiny1626’, ‘attiny1627’, ‘attiny3214’, ‘attiny3216’, ‘attiny3217’, ‘attiny3224’, ‘attiny3226’, ‘attiny3227’, ‘atmega808’, ‘atmega809’, ‘atmega1608’, ‘atmega1609’, ‘atmega3208’, ‘atmega3209’, ‘atmega4808’, ‘atmega4809’, ‘avr16dd14’, ‘avr16dd20’, ‘avr16dd28’, ‘avr16dd32’, ‘avr16ea28’, ‘avr16ea32’, ‘avr16ea48’, ‘avr16eb14’, ‘avr16eb20’, ‘avr16eb28’, ‘avr16eb32’, ‘avr32da28’, ‘avr32da32’, ‘avr32da48’, ‘avr32db28’, ‘avr32db32’, ‘avr32db48’, ‘avr32dd14’, ‘avr32dd20’, ‘avr32dd28’, ‘avr32dd32’, ‘avr32ea28’, ‘avr32ea32’, ‘avr32ea48’. ‘avrxmega4’ "XMEGA" devices with more than 64 KiB and up to 128 KiB of program memory. MCU = ‘atxmega64a3’, ‘atxmega64a3u’, ‘atxmega64a4u’, ‘atxmega64b1’, ‘atxmega64b3’, ‘atxmega64c3’, ‘atxmega64d3’, ‘atxmega64d4’, ‘avr128da28’, ‘avr128da32’, ‘avr128da48’, ‘avr128da64’, ‘avr128db28’, ‘avr128db32’, ‘avr128db48’, ‘avr128db64’. ‘avrxmega5’ "XMEGA" devices with more than 64 KiB and up to 128 KiB of program memory and more than 64 KiB of RAM. MCU = ‘atxmega64a1’, ‘atxmega64a1u’. ‘avrxmega6’ "XMEGA" devices with more than 128 KiB of program memory. MCU = ‘atxmega128a3’, ‘atxmega128a3u’, ‘atxmega128b1’, ‘atxmega128b3’, ‘atxmega128c3’, ‘atxmega128d3’, ‘atxmega128d4’, ‘atxmega192a3’, ‘atxmega192a3u’, ‘atxmega192c3’, ‘atxmega192d3’, ‘atxmega256a3’, ‘atxmega256a3b’, ‘atxmega256a3bu’, ‘atxmega256a3u’, ‘atxmega256c3’, ‘atxmega256d3’, ‘atxmega384c3’, ‘atxmega384d3’. ‘avrxmega7’ "XMEGA" devices with more than 128 KiB of program memory and more than 64 KiB of RAM. MCU = ‘atxmega128a1’, ‘atxmega128a1u’, ‘atxmega128a4u’. ‘avrtiny’ "Reduced Tiny" Tiny core devices with only 16 general purpose registers and 512 B up to 4 KiB of program memory. MCU = ‘attiny4’, ‘attiny5’, ‘attiny9’, ‘attiny10’, ‘attiny102’, ‘attiny104’, ‘attiny20’, ‘attiny40’. ‘avr1’ This ISA is implemented by the minimal AVR core and supported for assembler only. MCU = ‘attiny11’, ‘attiny12’, ‘attiny15’, ‘attiny28’, ‘at90s1200’. ‘-mabsdata’ Assume that all data in static storage can be accessed by LDS / STS instructions. This option has only an effect on reduced Tiny devices like ATtiny40. See also the ‘absdata’ *note variable attribute: AVR Variable Attributes. ‘-maccumulate-args’ Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments once in function prologue/epilogue. Without this option, outgoing arguments are pushed before calling a function and popped afterwards. Popping the arguments after the function call can be expensive on AVR so that accumulating the stack space might lead to smaller executables because arguments need not be removed from the stack after such a function call. This option can lead to reduced code size for functions that perform several calls to functions that get their arguments on the stack like calls to printf-like functions. ‘-mbranch-cost=COST’ Set the branch costs for conditional branch instructions to COST. Reasonable values for COST are small, non-negative integers. The default branch cost is 0. ‘-mcall-prologues’ Functions prologues/epilogues are expanded as calls to appropriate subroutines. Code size is smaller. ‘-mdouble=BITS’ ‘-mlong-double=BITS’ Set the size (in bits) of the ‘double’ or ‘long double’ type, respectively. Possible values for BITS are 32 and 64. Whether or not a specific value for BITS is allowed depends on the ‘--with-double=’ and ‘--with-long-double=’ configure options (https://gcc.gnu.org/install/configure.html#avr), and the same applies for the default values of the options. ‘-mgas-isr-prologues’ Interrupt service routines (ISRs) may use the ‘__gcc_isr’ pseudo instruction supported by GNU Binutils. If this option is on, the feature can still be disabled for individual ISRs by means of the *note ‘no_gccisr’: AVR Function Attributes. function attribute. This feature is activated per default if optimization is on (but not with ‘-Og’, *note Optimize Options::), and if GNU Binutils support PR21683 (https://sourceware.org/PR21683). ‘-mint8’ Assume ‘int’ to be 8-bit integer. This affects the sizes of all types: a ‘char’ is 1 byte, an ‘int’ is 1 byte, a ‘long’ is 2 bytes, and ‘long long’ is 4 bytes. Please note that this option does not conform to the C standards, but it results in smaller code size. ‘-mmain-is-OS_task’ Do not save registers in ‘main’. The effect is the same like attaching attribute *note ‘OS_task’: AVR Function Attributes. to ‘main’. It is activated per default if optimization is on. ‘-mno-interrupts’ Generated code is not compatible with hardware interrupts. Code size is smaller. ‘-mrelax’ Try to replace ‘CALL’ resp. ‘JMP’ instruction by the shorter ‘RCALL’ resp. ‘RJMP’ instruction if applicable. Setting ‘-mrelax’ just adds the ‘--mlink-relax’ option to the assembler's command line and the ‘--relax’ option to the linker's command line. Jump relaxing is performed by the linker because jump offsets are not known before code is located. Therefore, the assembler code generated by the compiler is the same, but the instructions in the executable may differ from instructions in the assembler code. Relaxing must be turned on if linker stubs are needed, see the section on ‘EIND’ and linker stubs below. ‘-mrodata-in-ram’ ‘-mno-rodata-in-ram’ Locate the ‘.rodata’ sections for read-only data in RAM resp. in program memory. For most devices, there is no choice and this option acts rather like an assertion. Since v14 and for the AVR64* and AVR128* devices, ‘.rodata’ is located in flash memory per default, provided the required GNU Binutils support (PR31124 (https://sourceware.org/PR31124)) is available. In that case, ‘-mrodata-in-ram’ can be used to return to the old layout with ‘.rodata’ in RAM. ‘-mstrict-X’ Use address register ‘X’ in a way proposed by the hardware. This means that ‘X’ is only used in indirect, post-increment or pre-decrement addressing. Without this option, the ‘X’ register may be used in the same way as ‘Y’ or ‘Z’ which then is emulated by additional instructions. For example, loading a value with ‘X+const’ addressing with a small non-negative ‘const < 64’ to a register RN is performed as adiw r26, const ; X += const ld RN, X ; RN = *X sbiw r26, const ; X -= const ‘-mtiny-stack’ Only change the lower 8 bits of the stack pointer. ‘-mfract-convert-truncate’ Allow to use truncation instead of rounding towards zero for fractional fixed-point types. ‘-nodevicelib’ Don't link against AVR-LibC's device specific library ‘lib.a’. ‘-nodevicespecs’ Don't add ‘-specs=device-specs/specs-MCU’ to the compiler driver's command line. The user takes responsibility for supplying the sub-processes like compiler proper, assembler and linker with appropriate command line options. This means that the user has to supply her private device specs file by means of ‘-specs=PATH-TO-SPECS-FILE’. There is no more need for option ‘-mmcu=MCU’. This option can also serve as a replacement for the older way of specifying custom device-specs files that needed ‘-B SOME-PATH’ to point to a directory which contains a folder named ‘device-specs’ which contains a specs file named ‘specs-MCU’, where MCU was specified by ‘-mmcu=MCU’. ‘-Waddr-space-convert’ Warn about conversions between address spaces in the case where the resulting address space is not contained in the incoming address space. ‘-Wmisspelled-isr’ Warn if the ISR is misspelled, i.e. without __vector prefix. Enabled by default. 3.19.6.1 ‘EIND’ and Devices with More Than 128 Ki Bytes of Flash ................................................................ Pointers in the implementation are 16 bits wide. The address of a function or label is represented as word address so that indirect jumps and calls can target any code address in the range of 64 Ki words. In order to facilitate indirect jump on devices with more than 128 Ki bytes of program memory space, there is a special function register called ‘EIND’ that serves as most significant part of the target address when ‘EICALL’ or ‘EIJMP’ instructions are used. Indirect jumps and calls on these devices are handled as follows by the compiler and are subject to some limitations: • The compiler never sets ‘EIND’. • The compiler uses ‘EIND’ implicitly in ‘EICALL’/‘EIJMP’ instructions or might read ‘EIND’ directly in order to emulate an indirect call/jump by means of a ‘RET’ instruction. • The compiler assumes that ‘EIND’ never changes during the startup code or during the application. In particular, ‘EIND’ is not saved/restored in function or interrupt service routine prologue/epilogue. • For indirect calls to functions and computed goto, the linker generates _stubs_. Stubs are jump pads sometimes also called _trampolines_. Thus, the indirect call/jump jumps to such a stub. The stub contains a direct jump to the desired address. • Linker relaxation must be turned on so that the linker generates the stubs correctly in all situations. See the compiler option ‘-mrelax’ and the linker option ‘--relax’. There are corner cases where the linker is supposed to generate stubs but aborts without relaxation and without a helpful error message. • The default linker script is arranged for code with ‘EIND = 0’. If code is supposed to work for a setup with ‘EIND != 0’, a custom linker script has to be used in order to place the sections whose name start with ‘.trampolines’ into the segment where ‘EIND’ points to. • The startup code from libgcc never sets ‘EIND’. Notice that startup code is a blend of code from libgcc and AVR-LibC. For the impact of AVR-LibC on ‘EIND’, see the AVR-LibC user manual (https://www.nongnu.org/avr-libc/user-manual/). • It is legitimate for user-specific startup code to set up ‘EIND’ early, for example by means of initialization code located in section ‘.init3’. Such code runs prior to general startup code that initializes RAM and calls constructors, but after the bit of startup code from AVR-LibC that sets ‘EIND’ to the segment where the vector table is located. #include static void __attribute__((section(".init3"),naked,used,no_instrument_function)) init3_set_eind (void) { __asm volatile ("ldi r24,pm_hh8(__trampolines_start)\n\t" "out %i0,r24" :: "n" (&EIND) : "r24","memory"); } The ‘__trampolines_start’ symbol is defined in the linker script. • Stubs are generated automatically by the linker if the following two conditions are met: − The address of a label is taken by means of the ‘gs’ modifier (short for _generate stubs_) like so: LDI r24, lo8(gs(FUNC)) LDI r25, hi8(gs(FUNC)) − The final location of that label is in a code segment _outside_ the segment where the stubs are located. • The compiler emits such ‘gs’ modifiers for code labels in the following situations: − Taking address of a function or code label. − Computed goto. − If prologue-save function is used, see ‘-mcall-prologues’ command-line option. − Switch/case dispatch tables. If you do not want such dispatch tables you can specify the ‘-fno-jump-tables’ command-line option. − C and C++ constructors/destructors called during startup/shutdown. − If the tools hit a ‘gs()’ modifier explained above. • Jumping to non-symbolic addresses like so is _not_ supported: int main (void) { /* Call function at word address 0x2 */ return ((int(*)(void)) 0x2)(); } Instead, a stub has to be set up, i.e. the function has to be called through a symbol (‘func_4’ in the example): int main (void) { extern int func_4 (void); /* Call function at byte address 0x4 */ return func_4(); } and the application be linked with ‘-Wl,--defsym,func_4=0x4’. Alternatively, ‘func_4’ can be defined in the linker script. 3.19.6.2 Handling of the ‘RAMPD’, ‘RAMPX’, ‘RAMPY’ and ‘RAMPZ’ Special Function Registers ......................................................................................... Some AVR devices support memories larger than the 64 KiB range that can be accessed with 16-bit pointers. To access memory locations outside this 64 KiB range, the content of a ‘RAMP’ register is used as high part of the address: The ‘X’, ‘Y’, ‘Z’ address register is concatenated with the ‘RAMPX’, ‘RAMPY’, ‘RAMPZ’ special function register, respectively, to get a wide address. Similarly, ‘RAMPD’ is used together with direct addressing. • The startup code initializes the ‘RAMP’ special function registers with zero. • If a *note named address space: AVR Named Address Spaces. other than generic or ‘__flash’ is used, then ‘RAMPZ’ is set as needed before the operation. • If the device supports RAM larger than 64 KiB and the compiler needs to change ‘RAMPZ’ to accomplish an operation, ‘RAMPZ’ is reset to zero after the operation. • If the device comes with a specific ‘RAMP’ register, the ISR prologue/epilogue saves/restores that SFR and initializes it with zero in case the ISR code might (implicitly) use it. • RAM larger than 64 KiB is not supported by GCC for AVR targets. If you use inline assembler to read from locations outside the 16-bit address range and change one of the ‘RAMP’ registers, you must reset it to zero after the access. 3.19.6.3 AVR Built-in Macros ............................ GCC defines several built-in macros so that the user code can test for the presence or absence of features. Almost any of the following built-in macros are deduced from device capabilities and thus triggered by the ‘-mmcu=’ command-line option. For even more AVR-specific built-in macros see *note AVR Named Address Spaces:: and *note AVR Built-in Functions::. ‘__AVR_ARCH__’ Build-in macro that resolves to a decimal number that identifies the architecture and depends on the ‘-mmcu=MCU’ option. Possible values are: ‘2’, ‘25’, ‘3’, ‘31’, ‘35’, ‘4’, ‘5’, ‘51’, ‘6’ for MCU=‘avr2’, ‘avr25’, ‘avr3’, ‘avr31’, ‘avr35’, ‘avr4’, ‘avr5’, ‘avr51’, ‘avr6’, respectively and ‘100’, ‘102’, ‘103’, ‘104’, ‘105’, ‘106’, ‘107’ for MCU=‘avrtiny’, ‘avrxmega2’, ‘avrxmega3’, ‘avrxmega4’, ‘avrxmega5’, ‘avrxmega6’, ‘avrxmega7’, respectively. If MCU specifies a device, this built-in macro is set accordingly. For example, with ‘-mmcu=atmega8’ the macro is defined to ‘4’. ‘__AVR_DEVICE__’ Setting ‘-mmcu=DEVICE’ defines this built-in macro which reflects the device's name. For example, ‘-mmcu=atmega8’ defines the built-in macro ‘__AVR_ATmega8__’, ‘-mmcu=attiny261a’ defines ‘__AVR_ATtiny261A__’, etc. The built-in macros' names follow the scheme ‘__AVR_DEVICE__’ where DEVICE is the device name as from the AVR user manual. The difference between DEVICE in the built-in macro and DEVICE in ‘-mmcu=DEVICE’ is that the latter is always lowercase. If DEVICE is not a device but only a core architecture like ‘avr51’, this macro is not defined. ‘__AVR_DEVICE_NAME__’ Setting ‘-mmcu=DEVICE’ defines this built-in macro to the device's name. For example, with ‘-mmcu=atmega8’ the macro is defined to ‘atmega8’. If DEVICE is not a device but only a core architecture like ‘avr51’, this macro is not defined. ‘__AVR_XMEGA__’ The device / architecture belongs to the XMEGA family of devices. ‘__AVR_HAVE_ADIW__’ The device has the ‘ADIW’ and ‘SBIW’ instructions. ‘__AVR_HAVE_ELPM__’ The device has the ‘ELPM’ instruction. ‘__AVR_HAVE_ELPMX__’ The device has the ‘ELPM RN,Z’ and ‘ELPM RN,Z+’ instructions. ‘__AVR_HAVE_LPMX__’ The device has the ‘LPM RN,Z’ and ‘LPM RN,Z+’ instructions. ‘__AVR_HAVE_MOVW__’ The device has the ‘MOVW’ instruction to perform 16-bit register-register moves. ‘__AVR_HAVE_MUL__’ The device has a hardware multiplier. ‘__AVR_HAVE_JMP_CALL__’ The device has the ‘JMP’ and ‘CALL’ instructions. This is the case for devices with more than 8 KiB of program memory. ‘__AVR_HAVE_EIJMP_EICALL__’ ‘__AVR_3_BYTE_PC__’ The device has the ‘EIJMP’ and ‘EICALL’ instructions. This is the case for devices with more than 128 KiB of program memory. This also means that the program counter (PC) is 3 bytes wide. ‘__AVR_2_BYTE_PC__’ The program counter (PC) is 2 bytes wide. This is the case for devices with up to 128 KiB of program memory. ‘__AVR_HAVE_8BIT_SP__’ ‘__AVR_HAVE_16BIT_SP__’ The stack pointer (SP) register is treated as 8-bit respectively 16-bit register by the compiler. The definition of these macros is affected by ‘-mtiny-stack’. ‘__AVR_HAVE_SPH__’ ‘__AVR_SP8__’ The device has the SPH (high part of stack pointer) special function register or has an 8-bit stack pointer, respectively. The definition of these macros is affected by ‘-mmcu=’ and in the cases of ‘-mmcu=avr2’ and ‘-mmcu=avr25’ also by ‘-msp8’. ‘__AVR_HAVE_RAMPD__’ ‘__AVR_HAVE_RAMPX__’ ‘__AVR_HAVE_RAMPY__’ ‘__AVR_HAVE_RAMPZ__’ The device has the ‘RAMPD’, ‘RAMPX’, ‘RAMPY’, ‘RAMPZ’ special function register, respectively. ‘__NO_INTERRUPTS__’ This macro reflects the ‘-mno-interrupts’ command-line option. ‘__AVR_ERRATA_SKIP__’ ‘__AVR_ERRATA_SKIP_JMP_CALL__’ Some AVR devices (AT90S8515, ATmega103) must not skip 32-bit instructions because of a hardware erratum. Skip instructions are ‘SBRS’, ‘SBRC’, ‘SBIS’, ‘SBIC’ and ‘CPSE’. The second macro is only defined if ‘__AVR_HAVE_JMP_CALL__’ is also set. ‘__AVR_ISA_RMW__’ The device has Read-Modify-Write instructions (XCH, LAC, LAS and LAT). ‘__AVR_SFR_OFFSET__=OFFSET’ Instructions that can address I/O special function registers directly like ‘IN’, ‘OUT’, ‘SBI’, etc. may use a different address as if addressed by an instruction to access RAM like ‘LD’ or ‘STS’. This offset depends on the device architecture and has to be subtracted from the RAM address in order to get the respective I/O address. ‘__AVR_SHORT_CALLS__’ The ‘-mshort-calls’ command line option is set. ‘__AVR_PM_BASE_ADDRESS__=ADDR’ Some devices support reading from flash memory by means of ‘LD*’ instructions. The flash memory is seen in the data address space at an offset of ‘__AVR_PM_BASE_ADDRESS__’. If this macro is not defined, this feature is not available. If defined, the address space is linear and there is no need to put ‘.rodata’ into RAM. This is handled by the default linker description file, and is currently available for ‘avrtiny’ and ‘avrxmega3’. Even more convenient, there is no need to use address spaces like ‘__flash’ or features like attribute ‘progmem’ and ‘pgm_read_*’. ‘__AVR_HAVE_FLMAP__’ This macro is defined provided the following conditions are met: • The device has the ‘NVMCTRL_CTRLB.FLMAP’ bitfield. This applies to the AVR64* and AVR128* devices. • It's not known at assembler-time which emulation will be used. This implies the compiler was configured with GNU Binutils that implement PR31124 (https://sourceware.org/PR31124). ‘__AVR_RODATA_IN_RAM__’ This macro is undefined when the code is compiled for a core architecture. When the code is compiled for a device, the macro is defined to 1 when the ‘.rodata’ sections for read-only data is located in RAM; and defined to 0, otherwise. ‘__WITH_AVRLIBC__’ The compiler is configured to be used together with AVR-Libc. See the ‘--with-avrlibc’ configure option. ‘__HAVE_DOUBLE_MULTILIB__’ Defined if ‘-mdouble=’ acts as a multilib option. ‘__HAVE_DOUBLE32__’ ‘__HAVE_DOUBLE64__’ Defined if the compiler supports 32-bit double resp. 64-bit double. The actual layout is specified by option ‘-mdouble=’. ‘__DEFAULT_DOUBLE__’ The size in bits of ‘double’ if ‘-mdouble=’ is not set. To test the layout of ‘double’ in a program, use the built-in macro ‘__SIZEOF_DOUBLE__’. ‘__HAVE_LONG_DOUBLE32__’ ‘__HAVE_LONG_DOUBLE64__’ ‘__HAVE_LONG_DOUBLE_MULTILIB__’ ‘__DEFAULT_LONG_DOUBLE__’ Same as above, but for ‘long double’ instead of ‘double’. ‘__WITH_DOUBLE_COMPARISON__’ Reflects the ‘--with-double-comparison={tristate|bool|libf7}’ configure option (https://gcc.gnu.org/install/configure.html#avr) and is defined to ‘2’ or ‘3’. ‘__WITH_LIBF7_LIBGCC__’ ‘__WITH_LIBF7_MATH__’ ‘__WITH_LIBF7_MATH_SYMBOLS__’ Reflects the ‘--with-libf7={libgcc|math|math-symbols}’ configure option (https://gcc.gnu.org/install/configure.html#avr). 3.19.6.4 AVR Internal Options ............................. The following options are used internally by the compiler and to communicate between device specs files and the compiler proper. You don't need to set these options by hand, in particular they are not optimization options. Using these options in the wrong way may lead to sub-optimal or wrong code. They are documented for completeness, and in order to get a better understanding of device specs (https://gcc.gnu.org/wiki/avr-gcc#spec-files) files. ‘-mn-flash=NUM’ Assume that the flash memory has a size of NUM times 64 KiB. This determines which ‘__flashN’ address spaces are available. ‘-mflmap’ The device has the ‘FLMAP’ bit field located in special function register ‘NVMCTRL_CTRLB’. ‘-mrmw’ Assume that the device supports the Read-Modify-Write instructions ‘XCH’, ‘LAC’, ‘LAS’ and ‘LAT’. ‘-mshort-calls’ Assume that ‘RJMP’ and ‘RCALL’ can target the whole program memory. This option is used for multilib generation and selection for the devices from architecture ‘avrxmega3’. ‘-mskip-bug’ Generate code without skips (‘CPSE’, ‘SBRS’, ‘SBRC’, ‘SBIS’, ‘SBIC’) over 32-bit instructions. ‘-msp8’ Treat the stack pointer register as an 8-bit register, i.e. assume the high byte of the stack pointer is zero. This option is used by the compiler to select and build multilibs for architectures ‘avr2’ and ‘avr25’. These architectures mix devices with and without ‘SPH’.  File: gcc.info, Node: Blackfin Options, Next: C6X Options, Prev: AVR Options, Up: Submodel Options 3.19.7 Blackfin Options ----------------------- ‘-mcpu=CPU[-SIREVISION]’ Specifies the name of the target Blackfin processor. Currently, CPU can be one of ‘bf512’, ‘bf514’, ‘bf516’, ‘bf518’, ‘bf522’, ‘bf523’, ‘bf524’, ‘bf525’, ‘bf526’, ‘bf527’, ‘bf531’, ‘bf532’, ‘bf533’, ‘bf534’, ‘bf536’, ‘bf537’, ‘bf538’, ‘bf539’, ‘bf542’, ‘bf544’, ‘bf547’, ‘bf548’, ‘bf549’, ‘bf542m’, ‘bf544m’, ‘bf547m’, ‘bf548m’, ‘bf549m’, ‘bf561’, ‘bf592’. The optional SIREVISION specifies the silicon revision of the target Blackfin processor. Any workarounds available for the targeted silicon revision are enabled. If SIREVISION is ‘none’, no workarounds are enabled. If SIREVISION is ‘any’, all workarounds for the targeted processor are enabled. The ‘__SILICON_REVISION__’ macro is defined to two hexadecimal digits representing the major and minor numbers in the silicon revision. If SIREVISION is ‘none’, the ‘__SILICON_REVISION__’ is not defined. If SIREVISION is ‘any’, the ‘__SILICON_REVISION__’ is defined to be ‘0xffff’. If this optional SIREVISION is not used, GCC assumes the latest known silicon revision of the targeted Blackfin processor. GCC defines a preprocessor macro for the specified CPU. For the ‘bfin-elf’ toolchain, this option causes the hardware BSP provided by libgloss to be linked in if ‘-msim’ is not given. Without this option, ‘bf532’ is used as the processor by default. Note that support for ‘bf561’ is incomplete. For ‘bf561’, only the preprocessor macro is defined. ‘-msim’ Specifies that the program will be run on the simulator. This causes the simulator BSP provided by libgloss to be linked in. This option has effect only for ‘bfin-elf’ toolchain. Certain other options, such as ‘-mid-shared-library’ and ‘-mfdpic’, imply ‘-msim’. ‘-momit-leaf-frame-pointer’ Don't keep the frame pointer in a register for leaf functions. This avoids the instructions to save, set up and restore frame pointers and makes an extra register available in leaf functions. ‘-mspecld-anomaly’ When enabled, the compiler ensures that the generated code does not contain speculative loads after jump instructions. If this option is used, ‘__WORKAROUND_SPECULATIVE_LOADS’ is defined. ‘-mno-specld-anomaly’ Don't generate extra code to prevent speculative loads from occurring. ‘-mcsync-anomaly’ When enabled, the compiler ensures that the generated code does not contain CSYNC or SSYNC instructions too soon after conditional branches. If this option is used, ‘__WORKAROUND_SPECULATIVE_SYNCS’ is defined. ‘-mno-csync-anomaly’ Don't generate extra code to prevent CSYNC or SSYNC instructions from occurring too soon after a conditional branch. ‘-mlow64k’ When enabled, the compiler is free to take advantage of the knowledge that the entire program fits into the low 64k of memory. ‘-mno-low64k’ Assume that the program is arbitrarily large. This is the default. ‘-mstack-check-l1’ Do stack checking using information placed into L1 scratchpad memory by the uClinux kernel. ‘-mid-shared-library’ Generate code that supports shared libraries via the library ID method. This allows for execute in place and shared libraries in an environment without virtual memory management. This option implies ‘-fPIC’. With a ‘bfin-elf’ target, this option implies ‘-msim’. ‘-mno-id-shared-library’ Generate code that doesn't assume ID-based shared libraries are being used. This is the default. ‘-mleaf-id-shared-library’ Generate code that supports shared libraries via the library ID method, but assumes that this library or executable won't link against any other ID shared libraries. That allows the compiler to use faster code for jumps and calls. ‘-mno-leaf-id-shared-library’ Do not assume that the code being compiled won't link against any ID shared libraries. Slower code is generated for jump and call insns. ‘-mshared-library-id=n’ Specifies the identification number of the ID-based shared library being compiled. Specifying a value of 0 generates more compact code; specifying other values forces the allocation of that number to the current library but is no more space- or time-efficient than omitting this option. ‘-msep-data’ Generate code that allows the data segment to be located in a different area of memory from the text segment. This allows for execute in place in an environment without virtual memory management by eliminating relocations against the text section. ‘-mno-sep-data’ Generate code that assumes that the data segment follows the text segment. This is the default. ‘-mlong-calls’ ‘-mno-long-calls’ Tells the compiler to perform function calls by first loading the address of the function into a register and then performing a subroutine call on this register. This switch is needed if the target function lies outside of the 24-bit addressing range of the offset-based version of subroutine call instruction. This feature is not enabled by default. Specifying ‘-mno-long-calls’ restores the default behavior. Note these switches have no effect on how the compiler generates code to handle function calls via function pointers. ‘-mfast-fp’ Link with the fast floating-point library. This library relaxes some of the IEEE floating-point standard's rules for checking inputs against Not-a-Number (NAN), in the interest of performance. ‘-minline-plt’ Enable inlining of PLT entries in function calls to functions that are not known to bind locally. It has no effect without ‘-mfdpic’. ‘-mmulticore’ Build a standalone application for multicore Blackfin processors. This option causes proper start files and link scripts supporting multicore to be used, and defines the macro ‘__BFIN_MULTICORE’. It can only be used with ‘-mcpu=bf561[-SIREVISION]’. This option can be used with ‘-mcorea’ or ‘-mcoreb’, which selects the one-application-per-core programming model. Without ‘-mcorea’ or ‘-mcoreb’, the single-application/dual-core programming model is used. In this model, the main function of Core B should be named as ‘coreb_main’. If this option is not used, the single-core application programming model is used. ‘-mcorea’ Build a standalone application for Core A of BF561 when using the one-application-per-core programming model. Proper start files and link scripts are used to support Core A, and the macro ‘__BFIN_COREA’ is defined. This option can only be used in conjunction with ‘-mmulticore’. ‘-mcoreb’ Build a standalone application for Core B of BF561 when using the one-application-per-core programming model. Proper start files and link scripts are used to support Core B, and the macro ‘__BFIN_COREB’ is defined. When this option is used, ‘coreb_main’ should be used instead of ‘main’. This option can only be used in conjunction with ‘-mmulticore’. ‘-msdram’ Build a standalone application for SDRAM. Proper start files and link scripts are used to put the application into SDRAM, and the macro ‘__BFIN_SDRAM’ is defined. The loader should initialize SDRAM before loading the application. ‘-micplb’ Assume that ICPLBs are enabled at run time. This has an effect on certain anomaly workarounds. For Linux targets, the default is to assume ICPLBs are enabled; for standalone applications the default is off.  File: gcc.info, Node: C6X Options, Next: CRIS Options, Prev: Blackfin Options, Up: Submodel Options 3.19.8 C6X Options ------------------ ‘-march=NAME’ This specifies the name of the target architecture. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. Permissible names are: ‘c62x’, ‘c64x’, ‘c64x+’, ‘c67x’, ‘c67x+’, ‘c674x’. ‘-mbig-endian’ Generate code for a big-endian target. ‘-mlittle-endian’ Generate code for a little-endian target. This is the default. ‘-msim’ Choose startup files and linker script suitable for the simulator. ‘-msdata=default’ Put small global and static data in the ‘.neardata’ section, which is pointed to by register ‘B14’. Put small uninitialized global and static data in the ‘.bss’ section, which is adjacent to the ‘.neardata’ section. Put small read-only data into the ‘.rodata’ section. The corresponding sections used for large pieces of data are ‘.fardata’, ‘.far’ and ‘.const’. ‘-msdata=all’ Put all data, not just small objects, into the sections reserved for small data, and use addressing relative to the ‘B14’ register to access them. ‘-msdata=none’ Make no use of the sections reserved for small data, and use absolute addresses to access all data. Put all initialized global and static data in the ‘.fardata’ section, and all uninitialized data in the ‘.far’ section. Put all constant data into the ‘.const’ section.  File: gcc.info, Node: CRIS Options, Next: C-SKY Options, Prev: C6X Options, Up: Submodel Options 3.19.9 CRIS Options ------------------- These options are defined specifically for the CRIS ports. ‘-march=ARCHITECTURE-TYPE’ ‘-mcpu=ARCHITECTURE-TYPE’ Generate code for the specified architecture. The choices for ARCHITECTURE-TYPE are ‘v3’, ‘v8’ and ‘v10’ for respectively ETRAX 4, ETRAX 100, and ETRAX 100 LX. Default is ‘v0’. ‘-mtune=ARCHITECTURE-TYPE’ Tune to ARCHITECTURE-TYPE everything applicable about the generated code, except for the ABI and the set of available instructions. The choices for ARCHITECTURE-TYPE are the same as for ‘-march=ARCHITECTURE-TYPE’. ‘-mmax-stack-frame=N’ Warn when the stack frame of a function exceeds N bytes. ‘-metrax4’ ‘-metrax100’ The options ‘-metrax4’ and ‘-metrax100’ are synonyms for ‘-march=v3’ and ‘-march=v8’ respectively. ‘-mmul-bug-workaround’ ‘-mno-mul-bug-workaround’ Work around a bug in the ‘muls’ and ‘mulu’ instructions for CPU models where it applies. This option is disabled by default. ‘-mpdebug’ Enable CRIS-specific verbose debug-related information in the assembly code. This option also has the effect of turning off the ‘#NO_APP’ formatted-code indicator to the assembler at the beginning of the assembly file. ‘-mcc-init’ Do not use condition-code results from previous instruction; always emit compare and test instructions before use of condition codes. ‘-mno-side-effects’ Do not emit instructions with side effects in addressing modes other than post-increment. ‘-mstack-align’ ‘-mno-stack-align’ ‘-mdata-align’ ‘-mno-data-align’ ‘-mconst-align’ ‘-mno-const-align’ These options (‘no-’ options) arrange (eliminate arrangements) for the stack frame, individual data and constants to be aligned for the maximum single data access size for the chosen CPU model. The default is to arrange for 32-bit alignment. ABI details such as structure layout are not affected by these options. ‘-m32-bit’ ‘-m16-bit’ ‘-m8-bit’ Similar to the stack- data- and const-align options above, these options arrange for stack frame, writable data and constants to all be 32-bit, 16-bit or 8-bit aligned. The default is 32-bit alignment. ‘-mno-prologue-epilogue’ ‘-mprologue-epilogue’ With ‘-mno-prologue-epilogue’, the normal function prologue and epilogue which set up the stack frame are omitted and no return instructions or return sequences are generated in the code. Use this option only together with visual inspection of the compiled code: no warnings or errors are generated when call-saved registers must be saved, or storage for local variables needs to be allocated. ‘-melf’ Legacy no-op option. ‘-sim’ This option arranges to link with input-output functions from a simulator library. Code, initialized data and zero-initialized data are allocated consecutively. ‘-sim2’ Like ‘-sim’, but pass linker options to locate initialized data at 0x40000000 and zero-initialized data at 0x80000000.  File: gcc.info, Node: C-SKY Options, Next: Darwin Options, Prev: CRIS Options, Up: Submodel Options 3.19.10 C-SKY Options --------------------- GCC supports these options when compiling for C-SKY V2 processors. ‘-march=ARCH’ Specify the C-SKY target architecture. Valid values for ARCH are: ‘ck801’, ‘ck802’, ‘ck803’, ‘ck807’, and ‘ck810’. The default is ‘ck810’. ‘-mcpu=CPU’ Specify the C-SKY target processor. Valid values for CPU are: ‘ck801’, ‘ck801t’, ‘ck802’, ‘ck802t’, ‘ck802j’, ‘ck803’, ‘ck803h’, ‘ck803t’, ‘ck803ht’, ‘ck803f’, ‘ck803fh’, ‘ck803e’, ‘ck803eh’, ‘ck803et’, ‘ck803eht’, ‘ck803ef’, ‘ck803efh’, ‘ck803ft’, ‘ck803eft’, ‘ck803efht’, ‘ck803r1’, ‘ck803hr1’, ‘ck803tr1’, ‘ck803htr1’, ‘ck803fr1’, ‘ck803fhr1’, ‘ck803er1’, ‘ck803ehr1’, ‘ck803etr1’, ‘ck803ehtr1’, ‘ck803efr1’, ‘ck803efhr1’, ‘ck803ftr1’, ‘ck803eftr1’, ‘ck803efhtr1’, ‘ck803s’, ‘ck803st’, ‘ck803se’, ‘ck803sf’, ‘ck803sef’, ‘ck803seft’, ‘ck807e’, ‘ck807ef’, ‘ck807’, ‘ck807f’, ‘ck810e’, ‘ck810et’, ‘ck810ef’, ‘ck810eft’, ‘ck810’, ‘ck810v’, ‘ck810f’, ‘ck810t’, ‘ck810fv’, ‘ck810tv’, ‘ck810ft’, and ‘ck810ftv’. ‘-mbig-endian’ ‘-EB’ ‘-mlittle-endian’ ‘-EL’ Select big- or little-endian code. The default is little-endian. ‘-mfloat-abi=NAME’ Specifies which floating-point ABI to use. Permissible values are: ‘soft’, ‘softfp’ and ‘hard’. Specifying ‘soft’ causes GCC to generate output containing library calls for floating-point operations. ‘softfp’ allows the generation of code using hardware floating-point instructions, but still uses the soft-float calling conventions. ‘hard’ allows generation of floating-point instructions and uses FPU-specific calling conventions. The default depends on the specific target configuration. Note that the hard-float and soft-float ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries. ‘-mhard-float’ ‘-msoft-float’ Select hardware or software floating-point implementations. The default is soft float. ‘-mdouble-float’ ‘-mno-double-float’ When ‘-mhard-float’ is in effect, enable generation of double-precision float instructions. This is the default except when compiling for CK803. ‘-mfdivdu’ ‘-mno-fdivdu’ When ‘-mhard-float’ is in effect, enable generation of ‘frecipd’, ‘fsqrtd’, and ‘fdivd’ instructions. This is the default except when compiling for CK803. ‘-mfpu=FPU’ Select the floating-point processor. This option can only be used with ‘-mhard-float’. Values for FPU are ‘fpv2_sf’ (equivalent to ‘-mno-double-float -mno-fdivdu’), ‘fpv2’ (‘-mdouble-float -mno-divdu’), and ‘fpv2_divd’ (‘-mdouble-float -mdivdu’). ‘-melrw’ ‘-mno-elrw’ Enable the extended ‘lrw’ instruction. This option defaults to on for CK801 and off otherwise. ‘-mistack’ ‘-mno-istack’ Enable interrupt stack instructions; the default is off. The ‘-mistack’ option is required to handle the ‘interrupt’ and ‘isr’ function attributes (*note C-SKY Function Attributes::). ‘-mmp’ Enable multiprocessor instructions; the default is off. ‘-mcp’ Enable coprocessor instructions; the default is off. ‘-mcache’ Enable coprocessor instructions; the default is off. ‘-msecurity’ Enable C-SKY security instructions; the default is off. ‘-mtrust’ Enable C-SKY trust instructions; the default is off. ‘-mdsp’ ‘-medsp’ ‘-mvdsp’ Enable C-SKY DSP, Enhanced DSP, or Vector DSP instructions, respectively. All of these options default to off. ‘-mdiv’ ‘-mno-div’ Generate divide instructions. Default is off. ‘-msmart’ ‘-mno-smart’ Generate code for Smart Mode, using only registers numbered 0-7 to allow use of 16-bit instructions. This option is ignored for CK801 where this is the required behavior, and it defaults to on for CK802. For other targets, the default is off. ‘-mhigh-registers’ ‘-mno-high-registers’ Generate code using the high registers numbered 16-31. This option is not supported on CK801, CK802, or CK803, and is enabled by default for other processors. ‘-manchor’ ‘-mno-anchor’ Generate code using global anchor symbol addresses. ‘-mpushpop’ ‘-mno-pushpop’ Generate code using ‘push’ and ‘pop’ instructions. This option defaults to on. ‘-mmultiple-stld’ ‘-mstm’ ‘-mno-multiple-stld’ ‘-mno-stm’ Generate code using ‘stm’ and ‘ldm’ instructions. This option isn't supported on CK801 but is enabled by default on other processors. ‘-mconstpool’ ‘-mno-constpool’ Create constant pools in the compiler instead of deferring it to the assembler. This option is the default and required for correct code generation on CK801 and CK802, and is optional on other processors. ‘-mstack-size’ ‘-mno-stack-size’ Emit ‘.stack_size’ directives for each function in the assembly output. This option defaults to off. ‘-mccrt’ ‘-mno-ccrt’ Generate code for the C-SKY compiler runtime instead of libgcc. This option defaults to off. ‘-mbranch-cost=N’ Set the branch costs to roughly ‘n’ instructions. The default is 1. ‘-msched-prolog’ ‘-mno-sched-prolog’ Permit scheduling of function prologue and epilogue sequences. Using this option can result in code that is not compliant with the C-SKY V2 ABI prologue requirements and that cannot be debugged or backtraced. It is disabled by default. ‘-msim’ Links the library libsemi.a which is in compatible with simulator. Applicable to ELF compiler only.  File: gcc.info, Node: Darwin Options, Next: DEC Alpha Options, Prev: C-SKY Options, Up: Submodel Options 3.19.11 Darwin Options ---------------------- These options are defined for all architectures running the Darwin operating system. FSF GCC on Darwin does not create "fat" object files; it creates an object file for the single architecture that GCC was built to target. Apple's GCC on Darwin does create "fat" files if multiple ‘-arch’ options are used; it does so by running the compiler or linker multiple times and joining the results together with ‘lipo’. The subtype of the file created (like ‘ppc7400’ or ‘ppc970’ or ‘i686’) is determined by the flags that specify the ISA that GCC is targeting, like ‘-mcpu’ or ‘-march’. The ‘-force_cpusubtype_ALL’ option can be used to override this. The Darwin tools vary in their behavior when presented with an ISA mismatch. The assembler, ‘as’, only permits instructions to be used that are valid for the subtype of the file it is generating, so you cannot put 64-bit instructions in a ‘ppc750’ object file. The linker for shared libraries, ‘/usr/bin/libtool’, fails and prints an error if asked to create a shared library with a less restrictive subtype than its input files (for instance, trying to put a ‘ppc970’ object file in a ‘ppc7400’ library). The linker for executables, ‘ld’, quietly gives the executable the most restrictive subtype of any of its input files. ‘-FDIR’ Add the framework directory DIR to the head of the list of directories to be searched for header files. These directories are interleaved with those specified by ‘-I’ options and are scanned in a left-to-right order. A framework directory is a directory with frameworks in it. A framework is a directory with a ‘Headers’ and/or ‘PrivateHeaders’ directory contained directly in it that ends in ‘.framework’. The name of a framework is the name of this directory excluding the ‘.framework’. Headers associated with the framework are found in one of those two directories, with ‘Headers’ being searched first. A subframework is a framework directory that is in a framework's ‘Frameworks’ directory. Includes of subframework headers can only appear in a header of a framework that contains the subframework, or in a sibling subframework header. Two subframeworks are siblings if they occur in the same framework. A subframework should not have the same name as a framework; a warning is issued if this is violated. Currently a subframework cannot have subframeworks; in the future, the mechanism may be extended to support this. The standard frameworks can be found in ‘/System/Library/Frameworks’ and ‘/Library/Frameworks’. An example include looks like ‘#include ’, where ‘Framework’ denotes the name of the framework and ‘header.h’ is found in the ‘PrivateHeaders’ or ‘Headers’ directory. ‘-iframeworkDIR’ Like ‘-F’ except the directory is a treated as a system directory. The main difference between this ‘-iframework’ and ‘-F’ is that with ‘-iframework’ the compiler does not warn about constructs contained within header files found via DIR. This option is valid only for the C family of languages. ‘-gused’ Emit debugging information for symbols that are used. For stabs debugging format, this enables ‘-feliminate-unused-debug-symbols’. This is by default ON. ‘-gfull’ Emit debugging information for all symbols and types. ‘-fconstant-cfstrings’ The ‘-fconstant-cfstrings’ is an alias for ‘-mconstant-cfstrings’. ‘-mconstant-cfstrings’ When the NeXT runtime is being used (the default on these systems), override any ‘-fconstant-string-class’ setting and cause ‘@"..."’ literals to be laid out as constant CoreFoundation strings. ‘-mmacosx-version-min=VERSION’ The earliest version of MacOS X that this executable will run on is VERSION. Typical values supported for VERSION include ‘12’, ‘10.12’, and ‘10.5.8’. If the compiler was built to use the system's headers by default, then the default for this option is the system version on which the compiler is running, otherwise the default is to make choices that are compatible with as many systems and code bases as possible. ‘-mkernel’ Enable kernel development mode. The ‘-mkernel’ option sets ‘-static’, ‘-fno-common’, ‘-fno-use-cxa-atexit’, ‘-fno-exceptions’, ‘-fno-non-call-exceptions’, ‘-fapple-kext’, ‘-fno-weak’ and ‘-fno-rtti’ where applicable. This mode also sets ‘-mno-altivec’, ‘-msoft-float’, ‘-fno-builtin’ and ‘-mlong-branch’ for PowerPC targets. ‘-mone-byte-bool’ Override the defaults for ‘bool’ so that ‘sizeof(bool)==1’. By default ‘sizeof(bool)’ is ‘4’ when compiling for Darwin/PowerPC and ‘1’ when compiling for Darwin/x86, so this option has no effect on x86. *Warning:* The ‘-mone-byte-bool’ switch causes GCC to generate code that is not binary compatible with code generated without that switch. Using this switch may require recompiling all other modules in a program, including system libraries. Use this switch to conform to a non-default data model. ‘-mfix-and-continue’ ‘-ffix-and-continue’ ‘-findirect-data’ Generate code suitable for fast turnaround development, such as to allow GDB to dynamically load ‘.o’ files into already-running programs. ‘-findirect-data’ and ‘-ffix-and-continue’ are provided for backwards compatibility. ‘-all_load’ Loads all members of static archive libraries. See man ld(1) for more information. ‘-arch_errors_fatal’ Cause the errors having to do with files that have the wrong architecture to be fatal. ‘-bind_at_load’ Causes the output file to be marked such that the dynamic linker will bind all undefined references when the file is loaded or launched. ‘-bundle’ Produce a Mach-o bundle format file. See man ld(1) for more information. ‘-bundle_loader EXECUTABLE’ This option specifies the EXECUTABLE that will load the build output file being linked. See man ld(1) for more information. ‘-dynamiclib’ When passed this option, GCC produces a dynamic library instead of an executable when linking, using the Darwin ‘libtool’ command. ‘-force_cpusubtype_ALL’ This causes GCC's output file to have the ‘ALL’ subtype, instead of one controlled by the ‘-mcpu’ or ‘-march’ option. ‘-nodefaultrpaths’ Do not add default run paths for the compiler library directories to executables, modules or dynamic libraries. On macOS 10.5 and later, the embedded runpath is added by default unless the user adds ‘-nodefaultrpaths’ to the link line. Run paths are needed (and therefore enforced) to build on macOS version 10.11 or later. ‘-allowable_client CLIENT_NAME’ ‘-client_name’ ‘-compatibility_version’ ‘-current_version’ ‘-dead_strip’ ‘-dependency-file’ ‘-dylib_file’ ‘-dylinker_install_name’ ‘-dynamic’ ‘-exported_symbols_list’ ‘-filelist’ ‘-flat_namespace’ ‘-force_flat_namespace’ ‘-headerpad_max_install_names’ ‘-image_base’ ‘-init’ ‘-install_name’ ‘-keep_private_externs’ ‘-multi_module’ ‘-multiply_defined’ ‘-multiply_defined_unused’ ‘-noall_load’ ‘-no_dead_strip_inits_and_terms’ ‘-nofixprebinding’ ‘-nomultidefs’ ‘-noprebind’ ‘-noseglinkedit’ ‘-pagezero_size’ ‘-prebind’ ‘-prebind_all_twolevel_modules’ ‘-private_bundle’ ‘-read_only_relocs’ ‘-sectalign’ ‘-sectobjectsymbols’ ‘-whyload’ ‘-seg1addr’ ‘-sectcreate’ ‘-sectobjectsymbols’ ‘-sectorder’ ‘-segaddr’ ‘-segs_read_only_addr’ ‘-segs_read_write_addr’ ‘-seg_addr_table’ ‘-seg_addr_table_filename’ ‘-seglinkedit’ ‘-segprot’ ‘-segs_read_only_addr’ ‘-segs_read_write_addr’ ‘-single_module’ ‘-static’ ‘-sub_library’ ‘-sub_umbrella’ ‘-twolevel_namespace’ ‘-umbrella’ ‘-undefined’ ‘-unexported_symbols_list’ ‘-weak_reference_mismatches’ ‘-whatsloaded’ These options are passed to the Darwin linker. The Darwin linker man page describes them in detail.  File: gcc.info, Node: DEC Alpha Options, Next: eBPF Options, Prev: Darwin Options, Up: Submodel Options 3.19.12 DEC Alpha Options ------------------------- These ‘-m’ options are defined for the DEC Alpha implementations: ‘-mno-soft-float’ ‘-msoft-float’ Use (do not use) the hardware floating-point instructions for floating-point operations. When ‘-msoft-float’ is specified, functions in ‘libgcc.a’ are used to perform floating-point operations. Unless they are replaced by routines that emulate the floating-point operations, or compiled in such a way as to call such emulations routines, these routines issue floating-point operations. If you are compiling for an Alpha without floating-point operations, you must ensure that the library is built so as not to call them. Note that Alpha implementations without floating-point operations are required to have floating-point registers. ‘-mfp-reg’ ‘-mno-fp-regs’ Generate code that uses (does not use) the floating-point register set. ‘-mno-fp-regs’ implies ‘-msoft-float’. If the floating-point register set is not used, floating-point operands are passed in integer registers as if they were integers and floating-point results are passed in ‘$0’ instead of ‘$f0’. This is a non-standard calling sequence, so any function with a floating-point argument or return value called by code compiled with ‘-mno-fp-regs’ must also be compiled with that option. A typical use of this option is building a kernel that does not use, and hence need not save and restore, any floating-point registers. ‘-mieee’ The Alpha architecture implements floating-point hardware optimized for maximum performance. It is mostly compliant with the IEEE floating-point standard. However, for full compliance, software assistance is required. This option generates code fully IEEE-compliant code _except_ that the INEXACT-FLAG is not maintained (see below). If this option is turned on, the preprocessor macro ‘_IEEE_FP’ is defined during compilation. The resulting code is less efficient but is able to correctly support denormalized numbers and exceptional IEEE values such as not-a-number and plus/minus infinity. Other Alpha compilers call this option ‘-ieee_with_no_inexact’. ‘-mieee-with-inexact’ This is like ‘-mieee’ except the generated code also maintains the IEEE INEXACT-FLAG. Turning on this option causes the generated code to implement fully-compliant IEEE math. In addition to ‘_IEEE_FP’, ‘_IEEE_FP_EXACT’ is defined as a preprocessor macro. On some Alpha implementations the resulting code may execute significantly slower than the code generated by default. Since there is very little code that depends on the INEXACT-FLAG, you should normally not specify this option. Other Alpha compilers call this option ‘-ieee_with_inexact’. ‘-mfp-trap-mode=TRAP-MODE’ This option controls what floating-point related traps are enabled. Other Alpha compilers call this option ‘-fptm TRAP-MODE’. The trap mode can be set to one of four values: ‘n’ This is the default (normal) setting. The only traps that are enabled are the ones that cannot be disabled in software (e.g., division by zero trap). ‘u’ In addition to the traps enabled by ‘n’, underflow traps are enabled as well. ‘su’ Like ‘u’, but the instructions are marked to be safe for software completion (see Alpha architecture manual for details). ‘sui’ Like ‘su’, but inexact traps are enabled as well. ‘-mfp-rounding-mode=ROUNDING-MODE’ Selects the IEEE rounding mode. Other Alpha compilers call this option ‘-fprm ROUNDING-MODE’. The ROUNDING-MODE can be one of: ‘n’ Normal IEEE rounding mode. Floating-point numbers are rounded towards the nearest machine number or towards the even machine number in case of a tie. ‘m’ Round towards minus infinity. ‘c’ Chopped rounding mode. Floating-point numbers are rounded towards zero. ‘d’ Dynamic rounding mode. A field in the floating-point control register (FPCR, see Alpha architecture reference manual) controls the rounding mode in effect. The C library initializes this register for rounding towards plus infinity. Thus, unless your program modifies the FPCR, ‘d’ corresponds to round towards plus infinity. ‘-mtrap-precision=TRAP-PRECISION’ In the Alpha architecture, floating-point traps are imprecise. This means without software assistance it is impossible to recover from a floating trap and program execution normally needs to be terminated. GCC can generate code that can assist operating system trap handlers in determining the exact location that caused a floating-point trap. Depending on the requirements of an application, different levels of precisions can be selected: ‘p’ Program precision. This option is the default and means a trap handler can only identify which program caused a floating-point exception. ‘f’ Function precision. The trap handler can determine the function that caused a floating-point exception. ‘i’ Instruction precision. The trap handler can determine the exact instruction that caused a floating-point exception. Other Alpha compilers provide the equivalent options called ‘-scope_safe’ and ‘-resumption_safe’. ‘-mieee-conformant’ This option marks the generated code as IEEE conformant. You must not use this option unless you also specify ‘-mtrap-precision=i’ and either ‘-mfp-trap-mode=su’ or ‘-mfp-trap-mode=sui’. Its only effect is to emit the line ‘.eflag 48’ in the function prologue of the generated assembly file. ‘-mbuild-constants’ Normally GCC examines a 32- or 64-bit integer constant to see if it can construct it from smaller constants in two or three instructions. If it cannot, it outputs the constant as a literal and generates code to load it from the data segment at run time. Use this option to require GCC to construct _all_ integer constants using code, even if it takes more instructions (the maximum is six). You typically use this option to build a shared library dynamic loader. Itself a shared library, it must relocate itself in memory before it can find the variables and constants in its own data segment. ‘-mbwx’ ‘-mno-bwx’ ‘-mcix’ ‘-mno-cix’ ‘-mfix’ ‘-mno-fix’ ‘-mmax’ ‘-mno-max’ Indicate whether GCC should generate code to use the optional BWX, CIX, FIX and MAX instruction sets. The default is to use the instruction sets supported by the CPU type specified via ‘-mcpu=’ option or that of the CPU on which GCC was built if none is specified. ‘-mfloat-vax’ ‘-mfloat-ieee’ Generate code that uses (does not use) VAX F and G floating-point arithmetic instead of IEEE single and double precision. ‘-mexplicit-relocs’ ‘-mno-explicit-relocs’ Older Alpha assemblers provided no way to generate symbol relocations except via assembler macros. Use of these macros does not allow optimal instruction scheduling. GNU binutils as of version 2.12 supports a new syntax that allows the compiler to explicitly mark which relocations should apply to which instructions. This option is mostly useful for debugging, as GCC detects the capabilities of the assembler when it is built and sets the default accordingly. ‘-msmall-data’ ‘-mlarge-data’ When ‘-mexplicit-relocs’ is in effect, static data is accessed via “gp-relative” relocations. When ‘-msmall-data’ is used, objects 8 bytes long or smaller are placed in a “small data area” (the ‘.sdata’ and ‘.sbss’ sections) and are accessed via 16-bit relocations off of the ‘$gp’ register. This limits the size of the small data area to 64KB, but allows the variables to be directly accessed via a single instruction. The default is ‘-mlarge-data’. With this option the data area is limited to just below 2GB. Programs that require more than 2GB of data must use ‘malloc’ or ‘mmap’ to allocate the data in the heap instead of in the program's data segment. When generating code for shared libraries, ‘-fpic’ implies ‘-msmall-data’ and ‘-fPIC’ implies ‘-mlarge-data’. ‘-msmall-text’ ‘-mlarge-text’ When ‘-msmall-text’ is used, the compiler assumes that the code of the entire program (or shared library) fits in 4MB, and is thus reachable with a branch instruction. When ‘-msmall-data’ is used, the compiler can assume that all local symbols share the same ‘$gp’ value, and thus reduce the number of instructions required for a function call from 4 to 1. The default is ‘-mlarge-text’. ‘-mcpu=CPU_TYPE’ Set the instruction set and instruction scheduling parameters for machine type CPU_TYPE. You can specify either the ‘EV’ style name or the corresponding chip number. GCC supports scheduling parameters for the EV4, EV5 and EV6 family of processors and chooses the default values for the instruction set from the processor you specify. If you do not specify a processor type, GCC defaults to the processor on which the compiler was built. Supported values for CPU_TYPE are ‘ev4’ ‘ev45’ ‘21064’ Schedules as an EV4 and has no instruction set extensions. ‘ev5’ ‘21164’ Schedules as an EV5 and has no instruction set extensions. ‘ev56’ ‘21164a’ Schedules as an EV5 and supports the BWX extension. ‘pca56’ ‘21164pc’ ‘21164PC’ Schedules as an EV5 and supports the BWX and MAX extensions. ‘ev6’ ‘21264’ Schedules as an EV6 and supports the BWX, FIX, and MAX extensions. ‘ev67’ ‘21264a’ Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions. Native toolchains also support the value ‘native’, which selects the best architecture option for the host processor. ‘-mcpu=native’ has no effect if GCC does not recognize the processor. ‘-mtune=CPU_TYPE’ Set only the instruction scheduling parameters for machine type CPU_TYPE. The instruction set is not changed. Native toolchains also support the value ‘native’, which selects the best architecture option for the host processor. ‘-mtune=native’ has no effect if GCC does not recognize the processor. ‘-mmemory-latency=TIME’ Sets the latency the scheduler should assume for typical memory references as seen by the application. This number is highly dependent on the memory access patterns used by the application and the size of the external cache on the machine. Valid options for TIME are ‘NUMBER’ A decimal number representing clock cycles. ‘L1’ ‘L2’ ‘L3’ ‘main’ The compiler contains estimates of the number of clock cycles for "typical" EV4 & EV5 hardware for the Level 1, 2 & 3 caches (also called Dcache, Scache, and Bcache), as well as to main memory. Note that L3 is only valid for EV5.  File: gcc.info, Node: eBPF Options, Next: FR30 Options, Prev: DEC Alpha Options, Up: Submodel Options 3.19.13 eBPF Options -------------------- ‘-mframe-limit=BYTES’ This specifies the hard limit for frame sizes, in bytes. Currently, the value that can be specified should be less than or equal to ‘32767’. Defaults to whatever limit is imposed by the version of the Linux kernel targeted. ‘-mbig-endian’ Generate code for a big-endian target. ‘-mlittle-endian’ Generate code for a little-endian target. This is the default. ‘-mjmpext’ ‘-mno-jmpext’ Enable or disable generation of extra conditional-branch instructions. Enabled for CPU v2 and above. ‘-mjmp32’ ‘-mno-jmp32’ Enable or disable generation of 32-bit jump instructions. Enabled for CPU v3 and above. ‘-malu32’ ‘-mno-alu32’ Enable or disable generation of 32-bit ALU instructions. Enabled for CPU v3 and above. ‘-mv3-atomics’ ‘-mno-v3-atomics’ Enable or disable instructions for general atomic operations introduced in CPU v3. Enabled for CPU v3 and above. ‘-mbswap’ ‘-mno-bswap’ Enable or disable byte swap instructions. Enabled for CPU v4 and above. ‘-msdiv’ ‘-mno-sdiv’ Enable or disable signed division and modulus instructions. Enabled for CPU v4 and above. ‘-msmov’ ‘-mno-smov’ Enable or disable sign-extending move and memory load instructions. Enabled for CPU v4 and above. ‘-mcpu=VERSION’ This specifies which version of the eBPF ISA to target. Newer versions may not be supported by all kernels. The default is ‘v4’. Supported values for VERSION are: ‘v1’ The first stable eBPF ISA with no special features or extensions. ‘v2’ Supports the jump extensions, as in ‘-mjmpext’. ‘v3’ All features of v2, plus: − 32-bit jump operations, as in ‘-mjmp32’ − 32-bit ALU operations, as in ‘-malu32’ − general atomic operations, as in ‘-mv3-atomics’ ‘v4’ All features of v3, plus: − Byte swap instructions, as in ‘-mbswap’ − Signed division and modulus instructions, as in ‘-msdiv’ − Sign-extending move and memory load instructions, as in ‘-msmov’ ‘-mco-re’ Enable BPF Compile Once - Run Everywhere (CO-RE) support. Requires and is implied by ‘-gbtf’. ‘-mno-co-re’ Disable BPF Compile Once - Run Everywhere (CO-RE) support. BPF CO-RE support is enabled by default when generating BTF debug information for the BPF target. ‘-mxbpf’ Generate code for an expanded version of BPF, which relaxes some of the restrictions imposed by the BPF architecture: − Save and restore callee-saved registers at function entry and exit, respectively. ‘-masm=DIALECT’ Outputs assembly instructions using eBPF selected DIALECT. The default is ‘normal’. Supported values for DIALECT are: ‘normal’ Outputs normal assembly dialect. ‘pseudoc’ Outputs pseudo-c assembly dialect.  File: gcc.info, Node: FR30 Options, Next: FT32 Options, Prev: eBPF Options, Up: Submodel Options 3.19.14 FR30 Options -------------------- These options are defined specifically for the FR30 port. ‘-msmall-model’ Use the small address space model. This can produce smaller code, but it does assume that all symbolic values and addresses fit into a 20-bit range. ‘-mno-lsim’ Assume that runtime support has been provided and so there is no need to include the simulator library (‘libsim.a’) on the linker command line.  File: gcc.info, Node: FT32 Options, Next: FRV Options, Prev: FR30 Options, Up: Submodel Options 3.19.15 FT32 Options -------------------- These options are defined specifically for the FT32 port. ‘-msim’ Specifies that the program will be run on the simulator. This causes an alternate runtime startup and library to be linked. You must not use this option when generating programs that will run on real hardware; you must provide your own runtime library for whatever I/O functions are needed. ‘-mlra’ Enable Local Register Allocation. This is still experimental for FT32, so by default the compiler uses standard reload. ‘-mnodiv’ Do not use div and mod instructions. ‘-mft32b’ Enable use of the extended instructions of the FT32B processor. ‘-mcompress’ Compress all code using the Ft32B code compression scheme. ‘-mnopm’ Do not generate code that reads program memory.  File: gcc.info, Node: FRV Options, Next: GNU/Linux Options, Prev: FT32 Options, Up: Submodel Options 3.19.16 FRV Options ------------------- ‘-mgpr-32’ Only use the first 32 general-purpose registers. ‘-mgpr-64’ Use all 64 general-purpose registers. ‘-mfpr-32’ Use only the first 32 floating-point registers. ‘-mfpr-64’ Use all 64 floating-point registers. ‘-mhard-float’ Use hardware instructions for floating-point operations. ‘-msoft-float’ Use library routines for floating-point operations. ‘-malloc-cc’ Dynamically allocate condition code registers. ‘-mfixed-cc’ Do not try to dynamically allocate condition code registers, only use ‘icc0’ and ‘fcc0’. ‘-mdword’ Change ABI to use double word insns. ‘-mno-dword’ Do not use double word instructions. ‘-mdouble’ Use floating-point double instructions. ‘-mno-double’ Do not use floating-point double instructions. ‘-mmedia’ Use media instructions. ‘-mno-media’ Do not use media instructions. ‘-mmuladd’ Use multiply and add/subtract instructions. ‘-mno-muladd’ Do not use multiply and add/subtract instructions. ‘-mfdpic’ Select the FDPIC ABI, which uses function descriptors to represent pointers to functions. Without any PIC/PIE-related options, it implies ‘-fPIE’. With ‘-fpic’ or ‘-fpie’, it assumes GOT entries and small data are within a 12-bit range from the GOT base address; with ‘-fPIC’ or ‘-fPIE’, GOT offsets are computed with 32 bits. With a ‘bfin-elf’ target, this option implies ‘-msim’. ‘-minline-plt’ Enable inlining of PLT entries in function calls to functions that are not known to bind locally. It has no effect without ‘-mfdpic’. It's enabled by default if optimizing for speed and compiling for shared libraries (i.e., ‘-fPIC’ or ‘-fpic’), or when an optimization option such as ‘-O3’ or above is present in the command line. ‘-mTLS’ Assume a large TLS segment when generating thread-local code. ‘-mtls’ Do not assume a large TLS segment when generating thread-local code. ‘-mgprel-ro’ Enable the use of ‘GPREL’ relocations in the FDPIC ABI for data that is known to be in read-only sections. It's enabled by default, except for ‘-fpic’ or ‘-fpie’: even though it may help make the global offset table smaller, it trades 1 instruction for 4. With ‘-fPIC’ or ‘-fPIE’, it trades 3 instructions for 4, one of which may be shared by multiple symbols, and it avoids the need for a GOT entry for the referenced symbol, so it's more likely to be a win. If it is not, ‘-mno-gprel-ro’ can be used to disable it. ‘-multilib-library-pic’ Link with the (library, not FD) pic libraries. It's implied by ‘-mlibrary-pic’, as well as by ‘-fPIC’ and ‘-fpic’ without ‘-mfdpic’. You should never have to use it explicitly. ‘-mlinked-fp’ Follow the EABI requirement of always creating a frame pointer whenever a stack frame is allocated. This option is enabled by default and can be disabled with ‘-mno-linked-fp’. ‘-mlong-calls’ Use indirect addressing to call functions outside the current compilation unit. This allows the functions to be placed anywhere within the 32-bit address space. ‘-malign-labels’ Try to align labels to an 8-byte boundary by inserting NOPs into the previous packet. This option only has an effect when VLIW packing is enabled. It doesn't create new packets; it merely adds NOPs to existing ones. ‘-mlibrary-pic’ Generate position-independent EABI code. ‘-macc-4’ Use only the first four media accumulator registers. ‘-macc-8’ Use all eight media accumulator registers. ‘-mpack’ Pack VLIW instructions. ‘-mno-pack’ Do not pack VLIW instructions. ‘-mno-eflags’ Do not mark ABI switches in e_flags. ‘-mcond-move’ Enable the use of conditional-move instructions (default). This switch is mainly for debugging the compiler and will likely be removed in a future version. ‘-mno-cond-move’ Disable the use of conditional-move instructions. This switch is mainly for debugging the compiler and will likely be removed in a future version. ‘-mscc’ Enable the use of conditional set instructions (default). This switch is mainly for debugging the compiler and will likely be removed in a future version. ‘-mno-scc’ Disable the use of conditional set instructions. This switch is mainly for debugging the compiler and will likely be removed in a future version. ‘-mcond-exec’ Enable the use of conditional execution (default). This switch is mainly for debugging the compiler and will likely be removed in a future version. ‘-mno-cond-exec’ Disable the use of conditional execution. This switch is mainly for debugging the compiler and will likely be removed in a future version. ‘-mvliw-branch’ Run a pass to pack branches into VLIW instructions (default). This switch is mainly for debugging the compiler and will likely be removed in a future version. ‘-mno-vliw-branch’ Do not run a pass to pack branches into VLIW instructions. This switch is mainly for debugging the compiler and will likely be removed in a future version. ‘-mmulti-cond-exec’ Enable optimization of ‘&&’ and ‘||’ in conditional execution (default). This switch is mainly for debugging the compiler and will likely be removed in a future version. ‘-mno-multi-cond-exec’ Disable optimization of ‘&&’ and ‘||’ in conditional execution. This switch is mainly for debugging the compiler and will likely be removed in a future version. ‘-mnested-cond-exec’ Enable nested conditional execution optimizations (default). This switch is mainly for debugging the compiler and will likely be removed in a future version. ‘-mno-nested-cond-exec’ Disable nested conditional execution optimizations. This switch is mainly for debugging the compiler and will likely be removed in a future version. ‘-moptimize-membar’ This switch removes redundant ‘membar’ instructions from the compiler-generated code. It is enabled by default. ‘-mno-optimize-membar’ This switch disables the automatic removal of redundant ‘membar’ instructions from the generated code. ‘-mtomcat-stats’ Cause gas to print out tomcat statistics. ‘-mcpu=CPU’ Select the processor type for which to generate code. Possible values are ‘frv’, ‘fr550’, ‘tomcat’, ‘fr500’, ‘fr450’, ‘fr405’, ‘fr400’, ‘fr300’ and ‘simple’.  File: gcc.info, Node: GNU/Linux Options, Next: H8/300 Options, Prev: FRV Options, Up: Submodel Options 3.19.17 GNU/Linux Options ------------------------- These ‘-m’ options are defined for GNU/Linux targets: ‘-mglibc’ Use the GNU C library. This is the default except on ‘*-*-linux-*uclibc*’, ‘*-*-linux-*musl*’ and ‘*-*-linux-*android*’ targets. ‘-muclibc’ Use uClibc C library. This is the default on ‘*-*-linux-*uclibc*’ targets. ‘-mmusl’ Use the musl C library. This is the default on ‘*-*-linux-*musl*’ targets. ‘-mbionic’ Use Bionic C library. This is the default on ‘*-*-linux-*android*’ targets. ‘-mandroid’ Compile code compatible with Android platform. This is the default on ‘*-*-linux-*android*’ targets. When compiling, this option enables ‘-mbionic’, ‘-fPIC’, ‘-fno-exceptions’ and ‘-fno-rtti’ by default. When linking, this option makes the GCC driver pass Android-specific options to the linker. Finally, this option causes the preprocessor macro ‘__ANDROID__’ to be defined. ‘-tno-android-cc’ Disable compilation effects of ‘-mandroid’, i.e., do not enable ‘-mbionic’, ‘-fPIC’, ‘-fno-exceptions’ and ‘-fno-rtti’ by default. ‘-tno-android-ld’ Disable linking effects of ‘-mandroid’, i.e., pass standard Linux linking options to the linker.  File: gcc.info, Node: H8/300 Options, Next: HPPA Options, Prev: GNU/Linux Options, Up: Submodel Options 3.19.18 H8/300 Options ---------------------- These ‘-m’ options are defined for the H8/300 implementations: ‘-mrelax’ Shorten some address references at link time, when possible; uses the linker option ‘-relax’. *Note ‘ld’ and the H8/300: (ld)H8/300, for a fuller description. ‘-mh’ Generate code for the H8/300H. ‘-ms’ Generate code for the H8S. ‘-mn’ Generate code for the H8S and H8/300H in the normal mode. This switch must be used either with ‘-mh’ or ‘-ms’. ‘-ms2600’ Generate code for the H8S/2600. This switch must be used with ‘-ms’. ‘-mexr’ Extended registers are stored on stack before execution of function with monitor attribute. Default option is ‘-mexr’. This option is valid only for H8S targets. ‘-mno-exr’ Extended registers are not stored on stack before execution of function with monitor attribute. Default option is ‘-mno-exr’. This option is valid only for H8S targets. ‘-mint32’ Make ‘int’ data 32 bits by default. ‘-malign-300’ On the H8/300H and H8S, use the same alignment rules as for the H8/300. The default for the H8/300H and H8S is to align longs and floats on 4-byte boundaries. ‘-malign-300’ causes them to be aligned on 2-byte boundaries. This option has no effect on the H8/300.  File: gcc.info, Node: HPPA Options, Next: IA-64 Options, Prev: H8/300 Options, Up: Submodel Options 3.19.19 HPPA Options -------------------- These ‘-m’ options are defined for the HPPA family of computers: ‘-march=ARCHITECTURE-TYPE’ Generate code for the specified architecture. The choices for ARCHITECTURE-TYPE are ‘1.0’ for PA 1.0, ‘1.1’ for PA 1.1, and ‘2.0’ for PA 2.0 processors. Refer to ‘/usr/lib/sched.models’ on an HP-UX system to determine the proper architecture option for your machine. Code compiled for lower numbered architectures runs on higher numbered architectures, but not the other way around. ‘-mpa-risc-1-0’ ‘-mpa-risc-1-1’ ‘-mpa-risc-2-0’ Synonyms for ‘-march=1.0’, ‘-march=1.1’, and ‘-march=2.0’ respectively. ‘-matomic-libcalls’ Generate libcalls for atomic loads and stores when sync libcalls are disabled. This option is enabled by default. It only affects the generation of atomic libcalls by the HPPA backend. Both the sync and ‘libatomic’ libcall implementations use locking. As a result, processor stores are not atomic with respect to other atomic operations. Processor loads up to DImode are atomic with respect to other atomic operations provided they are implemented as a single access. The PA-RISC architecture does not support any atomic operations in hardware except for the ‘ldcw’ instruction. Thus, all atomic support is implemented using sync and atomic libcalls. Sync libcall support is in ‘libgcc.a’. Atomic libcall support is in ‘libatomic’. This option generates ‘__atomic_exchange’ calls for atomic stores. It also provides special handling for atomic DImode accesses on 32-bit targets. ‘-mbig-switch’ Does nothing. Preserved for backward compatibility. ‘-mcaller-copies’ The caller copies function arguments passed by hidden reference. This option should be used with care as it is not compatible with the default 32-bit runtime. However, only aggregates larger than eight bytes are passed by hidden reference and the option provides better compatibility with OpenMP. ‘-mcoherent-ldcw’ Use ldcw/ldcd coherent cache-control hint. ‘-mdisable-fpregs’ Disable floating-point registers. Equivalent to ‘-msoft-float’. ‘-mdisable-indexing’ Prevent the compiler from using indexing address modes. This avoids some rather obscure problems when compiling MIG generated code under MACH. ‘-mfast-indirect-calls’ Generate code that assumes calls never cross space boundaries. This allows GCC to emit code that performs faster indirect calls. This option does not work in the presence of shared libraries or nested functions. ‘-mfixed-range=REGISTER-RANGE’ Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator cannot use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma. ‘-mgas’ Enable the use of assembler directives only GAS understands. ‘-mgnu-ld’ Use options specific to GNU ‘ld’. This passes ‘-shared’ to ‘ld’ when building a shared library. It is the default when GCC is configured, explicitly or implicitly, with the GNU linker. This option does not affect which ‘ld’ is called; it only changes what parameters are passed to that ‘ld’. The ‘ld’ that is called is determined by the ‘--with-ld’ configure option, GCC's program search path, and finally by the user's ‘PATH’. The linker used by GCC can be printed using ‘which `gcc -print-prog-name=ld`’. This option is only available on the 64-bit HP-UX GCC, i.e. configured with ‘hppa*64*-*-hpux*’. ‘-mhp-ld’ Use options specific to HP ‘ld’. This passes ‘-b’ to ‘ld’ when building a shared library and passes ‘+Accept TypeMismatch’ to ‘ld’ on all links. It is the default when GCC is configured, explicitly or implicitly, with the HP linker. This option does not affect which ‘ld’ is called; it only changes what parameters are passed to that ‘ld’. The ‘ld’ that is called is determined by the ‘--with-ld’ configure option, GCC's program search path, and finally by the user's ‘PATH’. The linker used by GCC can be printed using ‘which `gcc -print-prog-name=ld`’. This option is only available on the 64-bit HP-UX GCC, i.e. configured with ‘hppa*64*-*-hpux*’. ‘-mlinker-opt’ Enable the optimization pass in the HP-UX linker. Note this makes symbolic debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9 linkers in which they give bogus error messages when linking some programs. ‘-mlong-calls’ Generate code that uses long call sequences. This ensures that a call is always able to reach linker generated stubs. The default is to generate long calls only when the distance from the call site to the beginning of the function or translation unit, as the case may be, exceeds a predefined limit set by the branch type being used. The limits for normal calls are 7,600,000 and 240,000 bytes, respectively for the PA 2.0 and PA 1.X architectures. Sibcalls are always limited at 240,000 bytes. Distances are measured from the beginning of functions when using the ‘-ffunction-sections’ option, or when using the ‘-mgas’ and ‘-mno-portable-runtime’ options together under HP-UX with the SOM linker. It is normally not desirable to use this option as it degrades performance. However, it may be useful in large applications, particularly when partial linking is used to build the application. The types of long calls used depends on the capabilities of the assembler and linker, and the type of code being generated. The impact on systems that support long absolute calls, and long pic symbol-difference or pc-relative calls should be relatively small. However, an indirect call is used on 32-bit ELF systems in pic code and it is quite long. ‘-mlong-load-store’ Generate 3-instruction load and store sequences as sometimes required by the HP-UX 10 linker. This is equivalent to the ‘+k’ option to the HP compilers. ‘-mjump-in-delay’ This option is ignored and provided for compatibility purposes only. ‘-mno-space-regs’ Generate code that assumes the target has no space registers. This allows GCC to generate faster indirect calls and use unscaled index address modes. Such code is suitable for level 0 PA systems and kernels. ‘-mordered’ Assume memory references are ordered and barriers are not needed. ‘-mportable-runtime’ Use the portable calling conventions proposed by HP for ELF systems. ‘-mschedule=CPU-TYPE’ Schedule code according to the constraints for the machine type CPU-TYPE. The choices for CPU-TYPE are ‘700’ ‘7100’, ‘7100LC’, ‘7200’, ‘7300’ and ‘8000’. Refer to ‘/usr/lib/sched.models’ on an HP-UX system to determine the proper scheduling option for your machine. The default scheduling is ‘8000’. ‘-msio’ Generate the predefine, ‘_SIO’, for server IO. The default is ‘-mwsio’. This generates the predefines, ‘__hp9000s700’, ‘__hp9000s700__’ and ‘_WSIO’, for workstation IO. These options are available under HP-UX and HI-UX. ‘-msoft-float’ Generate output containing library calls for floating point. *Warning:* the requisite libraries are not available for all HPPA targets. Normally the facilities of the machine's usual C compiler are used, but this cannot be done directly in cross-compilation. You must make your own arrangements to provide suitable library functions for cross-compilation. ‘-msoft-float’ changes the calling convention in the output file; therefore, it is only useful if you compile _all_ of a program with this option. In particular, you need to compile ‘libgcc.a’, the library that comes with GCC, with ‘-msoft-float’ in order for this to work. ‘-msoft-mult’ Use software integer multiplication. This disables the use of the ‘xmpyu’ instruction. ‘-munix=UNIX-STD’ Generate compiler predefines and select a startfile for the specified UNIX standard. The choices for UNIX-STD are ‘93’, ‘95’ and ‘98’. ‘93’ is supported on all HP-UX versions. ‘95’ is available on HP-UX 10.10 and later. ‘98’ is available on HP-UX 11.11 and later. The default values are ‘93’ for HP-UX 10.00, ‘95’ for HP-UX 10.10 though to 11.00, and ‘98’ for HP-UX 11.11 and later. ‘-munix=93’ provides the same predefines as GCC 3.3 and 3.4. ‘-munix=95’ provides additional predefines for ‘XOPEN_UNIX’ and ‘_XOPEN_SOURCE_EXTENDED’, and the startfile ‘unix95.o’. ‘-munix=98’ provides additional predefines for ‘_XOPEN_UNIX’, ‘_XOPEN_SOURCE_EXTENDED’, ‘_INCLUDE__STDC_A1_SOURCE’ and ‘_INCLUDE_XOPEN_SOURCE_500’, and the startfile ‘unix98.o’. It is _important_ to note that this option changes the interfaces for various library routines. It also affects the operational behavior of the C library. Thus, _extreme_ care is needed in using this option. Library code that is intended to operate with more than one UNIX standard must test, set and restore the variable ‘__xpg4_extended_mask’ as appropriate. Most GNU software doesn't provide this capability. ‘-nolibdld’ Suppress the generation of link options to search libdld.sl when the ‘-static’ option is specified on HP-UX 10 and later. ‘-static’ The HP-UX implementation of setlocale in libc has a dependency on libdld.sl. There isn't an archive version of libdld.sl. Thus, when the ‘-static’ option is specified, special link options are needed to resolve this dependency. On HP-UX 10 and later, the GCC driver adds the necessary options to link with libdld.sl when the ‘-static’ option is specified. This causes the resulting binary to be dynamic. On the 64-bit port, the linkers generate dynamic binaries by default in any case. The ‘-nolibdld’ option can be used to prevent the GCC driver from adding these link options. ‘-threads’ Add support for multithreading with the “dce thread” library under HP-UX. This option sets flags for both the preprocessor and linker.  File: gcc.info, Node: IA-64 Options, Next: LM32 Options, Prev: HPPA Options, Up: Submodel Options 3.19.20 IA-64 Options --------------------- These are the ‘-m’ options defined for the Intel IA-64 architecture. ‘-mbig-endian’ Generate code for a big-endian target. This is the default for HP-UX. ‘-mlittle-endian’ Generate code for a little-endian target. This is the default for AIX5 and GNU/Linux. ‘-mgnu-as’ ‘-mno-gnu-as’ Generate (or don't) code for the GNU assembler. This is the default. ‘-mgnu-ld’ ‘-mno-gnu-ld’ Generate (or don't) code for the GNU linker. This is the default. ‘-mno-pic’ Generate code that does not use a global pointer register. The result is not position independent code, and violates the IA-64 ABI. ‘-mvolatile-asm-stop’ ‘-mno-volatile-asm-stop’ Generate (or don't) a stop bit immediately before and after volatile asm statements. ‘-mregister-names’ ‘-mno-register-names’ Generate (or don't) ‘in’, ‘loc’, and ‘out’ register names for the stacked registers. This may make assembler output more readable. ‘-mno-sdata’ ‘-msdata’ Disable (or enable) optimizations that use the small data section. This may be useful for working around optimizer bugs. ‘-mconstant-gp’ Generate code that uses a single constant global pointer value. This is useful when compiling kernel code. ‘-mauto-pic’ Generate code that is self-relocatable. This implies ‘-mconstant-gp’. This is useful when compiling firmware code. ‘-minline-float-divide-min-latency’ Generate code for inline divides of floating-point values using the minimum latency algorithm. ‘-minline-float-divide-max-throughput’ Generate code for inline divides of floating-point values using the maximum throughput algorithm. ‘-mno-inline-float-divide’ Do not generate inline code for divides of floating-point values. ‘-minline-int-divide-min-latency’ Generate code for inline divides of integer values using the minimum latency algorithm. ‘-minline-int-divide-max-throughput’ Generate code for inline divides of integer values using the maximum throughput algorithm. ‘-mno-inline-int-divide’ Do not generate inline code for divides of integer values. ‘-minline-sqrt-min-latency’ Generate code for inline square roots using the minimum latency algorithm. ‘-minline-sqrt-max-throughput’ Generate code for inline square roots using the maximum throughput algorithm. ‘-mno-inline-sqrt’ Do not generate inline code for ‘sqrt’. ‘-mfused-madd’ ‘-mno-fused-madd’ Do (don't) generate code that uses the fused multiply/add or multiply/subtract instructions. The default is to use these instructions. ‘-mno-dwarf2-asm’ ‘-mdwarf2-asm’ Don't (or do) generate assembler code for the DWARF line number debugging info. This may be useful when not using the GNU assembler. ‘-mearly-stop-bits’ ‘-mno-early-stop-bits’ Allow stop bits to be placed earlier than immediately preceding the instruction that triggered the stop bit. This can improve instruction scheduling, but does not always do so. ‘-mfixed-range=REGISTER-RANGE’ Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator cannot use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma. ‘-mtls-size=TLS-SIZE’ Specify bit size of immediate TLS offsets. Valid values are 14, 22, and 64. ‘-mtune=CPU-TYPE’ Tune the instruction scheduling for a particular CPU, Valid values are ‘itanium’, ‘itanium1’, ‘merced’, ‘itanium2’, and ‘mckinley’. ‘-milp32’ ‘-mlp64’ Generate code for a 32-bit or 64-bit environment. The 32-bit environment sets int, long and pointer to 32 bits. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits. These are HP-UX specific flags. ‘-mno-sched-br-data-spec’ ‘-msched-br-data-spec’ (Dis/En)able data speculative scheduling before reload. This results in generation of ‘ld.a’ instructions and the corresponding check instructions (‘ld.c’ / ‘chk.a’). The default setting is disabled. ‘-msched-ar-data-spec’ ‘-mno-sched-ar-data-spec’ (En/Dis)able data speculative scheduling after reload. This results in generation of ‘ld.a’ instructions and the corresponding check instructions (‘ld.c’ / ‘chk.a’). The default setting is enabled. ‘-mno-sched-control-spec’ ‘-msched-control-spec’ (Dis/En)able control speculative scheduling. This feature is available only during region scheduling (i.e. before reload). This results in generation of the ‘ld.s’ instructions and the corresponding check instructions ‘chk.s’. The default setting is disabled. ‘-msched-br-in-data-spec’ ‘-mno-sched-br-in-data-spec’ (En/Dis)able speculative scheduling of the instructions that are dependent on the data speculative loads before reload. This is effective only with ‘-msched-br-data-spec’ enabled. The default setting is enabled. ‘-msched-ar-in-data-spec’ ‘-mno-sched-ar-in-data-spec’ (En/Dis)able speculative scheduling of the instructions that are dependent on the data speculative loads after reload. This is effective only with ‘-msched-ar-data-spec’ enabled. The default setting is enabled. ‘-msched-in-control-spec’ ‘-mno-sched-in-control-spec’ (En/Dis)able speculative scheduling of the instructions that are dependent on the control speculative loads. This is effective only with ‘-msched-control-spec’ enabled. The default setting is enabled. ‘-mno-sched-prefer-non-data-spec-insns’ ‘-msched-prefer-non-data-spec-insns’ If enabled, data-speculative instructions are chosen for schedule only if there are no other choices at the moment. This makes the use of the data speculation much more conservative. The default setting is disabled. ‘-mno-sched-prefer-non-control-spec-insns’ ‘-msched-prefer-non-control-spec-insns’ If enabled, control-speculative instructions are chosen for schedule only if there are no other choices at the moment. This makes the use of the control speculation much more conservative. The default setting is disabled. ‘-mno-sched-count-spec-in-critical-path’ ‘-msched-count-spec-in-critical-path’ If enabled, speculative dependencies are considered during computation of the instructions priorities. This makes the use of the speculation a bit more conservative. The default setting is disabled. ‘-msched-spec-ldc’ Use a simple data speculation check. This option is on by default. ‘-msched-control-spec-ldc’ Use a simple check for control speculation. This option is on by default. ‘-msched-stop-bits-after-every-cycle’ Place a stop bit after every cycle when scheduling. This option is on by default. ‘-msched-fp-mem-deps-zero-cost’ Assume that floating-point stores and loads are not likely to cause a conflict when placed into the same instruction group. This option is disabled by default. ‘-msel-sched-dont-check-control-spec’ Generate checks for control speculation in selective scheduling. This flag is disabled by default. ‘-msched-max-memory-insns=MAX-INSNS’ Limit on the number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same instruction group. Frequently useful to prevent cache bank conflicts. The default value is 1. ‘-msched-max-memory-insns-hard-limit’ Makes the limit specified by ‘msched-max-memory-insns’ a hard limit, disallowing more than that number in an instruction group. Otherwise, the limit is "soft", meaning that non-memory operations are preferred when the limit is reached, but memory operations may still be scheduled.  File: gcc.info, Node: LM32 Options, Next: LoongArch Options, Prev: IA-64 Options, Up: Submodel Options 3.19.21 LM32 Options -------------------- These ‘-m’ options are defined for the LatticeMico32 architecture: ‘-mbarrel-shift-enabled’ Enable barrel-shift instructions. ‘-mdivide-enabled’ Enable divide and modulus instructions. ‘-mmultiply-enabled’ Enable multiply instructions. ‘-msign-extend-enabled’ Enable sign extend instructions. ‘-muser-enabled’ Enable user-defined instructions.  File: gcc.info, Node: LoongArch Options, Next: M32C Options, Prev: LM32 Options, Up: Submodel Options 3.19.22 LoongArch Options ------------------------- These command-line options are defined for LoongArch targets: ‘-march=CPU-TYPE’ Generate instructions for the machine type CPU-TYPE. In contrast to ‘-mtune=CPU-TYPE’, which merely tunes the generated code for the specified CPU-TYPE, ‘-march=CPU-TYPE’ allows GCC to generate code that may not run at all on processors other than the one indicated. Specifying ‘-march=CPU-TYPE’ implies ‘-mtune=CPU-TYPE’, except where noted otherwise. The choices for CPU-TYPE are: ‘native’ This selects the CPU to generate code for at compilation time by determining the processor type of the compiling machine. Using ‘-march=native’ enables all instruction subsets supported by the local machine (hence the result might not run on different machines). Using ‘-mtune=native’ produces code optimized for the local machine under the constraints of the selected instruction set. ‘loongarch64’ A generic CPU with 64-bit extensions. ‘la464’ LoongArch LA464 CPU with LBT, LSX, LASX, LVZ. ‘-mtune=CPU-TYPE’ Optimize the output for the given processor, specified by microarchitecture name. ‘-mabi=BASE-ABI-TYPE’ Generate code for the specified calling convention. BASE-ABI-TYPE can be one of: ‘lp64d’ Uses 64-bit general purpose registers and 32/64-bit floating-point registers for parameter passing. Data model is LP64, where ‘int’ is 32 bits, while ‘long int’ and pointers are 64 bits. ‘lp64f’ Uses 64-bit general purpose registers and 32-bit floating-point registers for parameter passing. Data model is LP64, where ‘int’ is 32 bits, while ‘long int’ and pointers are 64 bits. ‘lp64s’ Uses 64-bit general purpose registers and no floating-point registers for parameter passing. Data model is LP64, where ‘int’ is 32 bits, while ‘long int’ and pointers are 64 bits. ‘-mfpu=FPU-TYPE’ Generate code for the specified FPU type, which can be one of: ‘64’ Allow the use of hardware floating-point instructions for 32-bit and 64-bit operations. ‘32’ Allow the use of hardware floating-point instructions for 32-bit operations. ‘none’ ‘0’ Prevent the use of hardware floating-point instructions. ‘-msimd=SIMD-TYPE’ Enable generation of LoongArch SIMD instructions for vectorization and via builtin functions. The value can be one of: ‘lasx’ Enable generating instructions from the 256-bit LoongArch Advanced SIMD Extension (LASX) and the 128-bit LoongArch SIMD Extension (LSX). ‘lsx’ Enable generating instructions from the 128-bit LoongArch SIMD Extension (LSX). ‘none’ No LoongArch SIMD instruction may be generated. ‘-msoft-float’ Force ‘-mfpu=none’ and prevents the use of floating-point registers for parameter passing. This option may change the target ABI. ‘-msingle-float’ Force ‘-mfpu=32’ and allow the use of 32-bit floating-point registers for parameter passing. This option may change the target ABI. ‘-mdouble-float’ Force ‘-mfpu=64’ and allow the use of 32/64-bit floating-point registers for parameter passing. This option may change the target ABI. ‘-mlasx’ ‘-mno-lasx’ ‘-mlsx’ ‘-mno-lsx’ Incrementally adjust the scope of the SIMD extensions (none / LSX / LASX) that can be used by the compiler for code generation. Enabling LASX with ‘mlasx’ automatically enables LSX, and diabling LSX with ‘mno-lsx’ automatically disables LASX. These driver-only options act upon the final ‘msimd’ configuration state and make incremental chagnes in the order they appear on the GCC driver's command line, deriving the final / canonicalized ‘msimd’ option that is passed to the compiler proper. ‘-mbranch-cost=N’ Set the cost of branches to roughly N instructions. ‘-mcheck-zero-division’ ‘-mno-check-zero-divison’ Trap (do not trap) on integer division by zero. The default is ‘-mcheck-zero-division’ for ‘-O0’ or ‘-Og’, and ‘-mno-check-zero-division’ for other optimization levels. ‘-mcond-move-int’ ‘-mno-cond-move-int’ Conditional moves for integral data in general-purpose registers are enabled (disabled). The default is ‘-mcond-move-int’. ‘-mcond-move-float’ ‘-mno-cond-move-float’ Conditional moves for floating-point registers are enabled (disabled). The default is ‘-mcond-move-float’. ‘-mmemcpy’ ‘-mno-memcpy’ Force (do not force) the use of ‘memcpy’ for non-trivial block moves. The default is ‘-mno-memcpy’, which allows GCC to inline most constant-sized copies. Setting optimization level to ‘-Os’ also forces the use of ‘memcpy’, but ‘-mno-memcpy’ may override this behavior if explicitly specified, regardless of the order these options on the command line. ‘-mstrict-align’ ‘-mno-strict-align’ Avoid or allow generating memory accesses that may not be aligned on a natural object boundary as described in the architecture specification. The default is ‘-mno-strict-align’. ‘-msmall-data-limit=NUMBER’ Put global and static data smaller than NUMBER bytes into a special section (on some targets). The default value is 0. ‘-mmax-inline-memcpy-size=N’ Inline all block moves (such as calls to ‘memcpy’ or structure copies) less than or equal to N bytes. The default value of N is 1024. ‘-mcmodel=CODE-MODEL’ Set the code model to one of: ‘tiny-static (Not implemented yet)’ ‘tiny (Not implemented yet)’ ‘normal’ The text segment must be within 128MB addressing space. The data segment must be within 2GB addressing space. ‘medium’ The text segment and data segment must be within 2GB addressing space. ‘large (Not implemented yet)’ ‘extreme’ This mode does not limit the size of the code segment and data segment. The ‘-mcmodel=extreme’ option is incompatible with ‘-fplt’ and/or ‘-mexplicit-relocs=none’. The default code model is ‘normal’. ‘-mexplicit-relocs=STYLE’ Set when to use assembler relocation operators when dealing with symbolic addresses. The alternative is to use assembler macros instead, which may limit instruction scheduling but allow linker relaxation. with ‘-mexplicit-relocs=none’ the assembler macros are always used, with ‘-mexplicit-relocs=always’ the assembler relocation operators are always used, with ‘-mexplicit-relocs=auto’ the compiler will use the relocation operators where the linker relaxation is impossible to improve the code quality, and macros elsewhere. The default value for the option is determined with the assembler capability detected during GCC build-time and the setting of ‘-mrelax’: ‘-mexplicit-relocs=none’ if the assembler does not support relocation operators at all, ‘-mexplicit-relocs=always’ if the assembler supports relocation operators but ‘-mrelax’ is not enabled, ‘-mexplicit-relocs=auto’ if the assembler supports relocation operators and ‘-mrelax’ is enabled. ‘-mexplicit-relocs’ An alias of ‘-mexplicit-relocs=always’ for backward compatibility. ‘-mno-explicit-relocs’ An alias of ‘-mexplicit-relocs=none’ for backward compatibility. ‘-mdirect-extern-access’ ‘-mno-direct-extern-access’ Do not use or use GOT to access external symbols. The default is ‘-mno-direct-extern-access’: GOT is used for external symbols with default visibility, but not used for other external symbols. With ‘-mdirect-extern-access’, GOT is not used and all external symbols are PC-relatively addressed. It is *only* suitable for environments where no dynamic link is performed, like firmwares, OS kernels, executables linked with ‘-static’ or ‘-static-pie’. ‘-mdirect-extern-access’ is not compatible with ‘-fPIC’ or ‘-fpic’. ‘-mrelax’ ‘-mno-relax’ Take (do not take) advantage of linker relaxations. If ‘-mpass-mrelax-to-as’ is enabled, this option is also passed to the assembler. The default is determined during GCC build-time by detecting corresponding assembler support: ‘-mrelax’ if the assembler supports both the ‘-mrelax’ option and the conditional branch relaxation (it's required or the ‘.align’ directives and conditional branch instructions in the assembly code outputted by GCC may be rejected by the assembler because of a relocation overflow), ‘-mno-relax’ otherwise. ‘-mpass-mrelax-to-as’ ‘-mno-pass-mrelax-to-as’ Pass (do not pass) the ‘-mrelax’ or ‘-mno-relax’ option to the assembler. The default is determined during GCC build-time by detecting corresponding assembler support: ‘-mpass-mrelax-to-as’ if the assembler supports the ‘-mrelax’ option, ‘-mno-pass-mrelax-to-as’ otherwise. This option is mostly useful for debugging, or interoperation with assemblers different from the build-time one. ‘-mrecip’ This option enables use of the reciprocal estimate and reciprocal square root estimate instructions with additional Newton-Raphson steps to increase precision instead of doing a divide or square root and divide for floating-point arguments. These instructions are generated only when ‘-funsafe-math-optimizations’ is enabled together with ‘-ffinite-math-only’ and ‘-fno-trapping-math’. This option is off by default. Before you can use this option, you must sure the target CPU supports frecipe and frsqrte instructions. Note that while the throughput of the sequence is higher than the throughput of the non-reciprocal instruction, the precision of the sequence can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994). ‘-mrecip=OPT’ This option controls which reciprocal estimate instructions may be used. OPT is a comma-separated list of options, which may be preceded by a ‘!’ to invert the option: ‘all’ Enable all estimate instructions. ‘default’ Enable the default instructions, equivalent to ‘-mrecip’. ‘none’ Disable all estimate instructions, equivalent to ‘-mno-recip’. ‘div’ Enable the approximation for scalar division. ‘vec-div’ Enable the approximation for vectorized division. ‘sqrt’ Enable the approximation for scalar square root. ‘vec-sqrt’ Enable the approximation for vectorized square root. ‘rsqrt’ Enable the approximation for scalar reciprocal square root. ‘vec-rsqrt’ Enable the approximation for vectorized reciprocal square root. So, for example, ‘-mrecip=all,!sqrt’ enables all of the reciprocal approximations, except for scalar square root. ‘loongarch-vect-unroll-limit’ The vectorizer will use available tuning information to determine whether it would be beneficial to unroll the main vectorized loop and by how much. This parameter set's the upper bound of how much the vectorizer will unroll the main loop. The default value is six.  File: gcc.info, Node: M32C Options, Next: M32R/D Options, Prev: LoongArch Options, Up: Submodel Options 3.19.23 M32C Options -------------------- ‘-mcpu=NAME’ Select the CPU for which code is generated. NAME may be one of ‘r8c’ for the R8C/Tiny series, ‘m16c’ for the M16C (up to /60) series, ‘m32cm’ for the M16C/80 series, or ‘m32c’ for the M32C/80 series. ‘-msim’ Specifies that the program will be run on the simulator. This causes an alternate runtime library to be linked in which supports, for example, file I/O. You must not use this option when generating programs that will run on real hardware; you must provide your own runtime library for whatever I/O functions are needed. ‘-memregs=NUMBER’ Specifies the number of memory-based pseudo-registers GCC uses during code generation. These pseudo-registers are used like real registers, so there is a tradeoff between GCC's ability to fit the code into available registers, and the performance penalty of using memory instead of registers. Note that all modules in a program must be compiled with the same value for this option. Because of that, you must not use this option with GCC's default runtime libraries.  File: gcc.info, Node: M32R/D Options, Next: M680x0 Options, Prev: M32C Options, Up: Submodel Options 3.19.24 M32R/D Options ---------------------- These ‘-m’ options are defined for Renesas M32R/D architectures: ‘-m32r2’ Generate code for the M32R/2. ‘-m32rx’ Generate code for the M32R/X. ‘-m32r’ Generate code for the M32R. This is the default. ‘-mmodel=small’ Assume all objects live in the lower 16MB of memory (so that their addresses can be loaded with the ‘ld24’ instruction), and assume all subroutines are reachable with the ‘bl’ instruction. This is the default. The addressability of a particular object can be set with the ‘model’ attribute. ‘-mmodel=medium’ Assume objects may be anywhere in the 32-bit address space (the compiler generates ‘seth/add3’ instructions to load their addresses), and assume all subroutines are reachable with the ‘bl’ instruction. ‘-mmodel=large’ Assume objects may be anywhere in the 32-bit address space (the compiler generates ‘seth/add3’ instructions to load their addresses), and assume subroutines may not be reachable with the ‘bl’ instruction (the compiler generates the much slower ‘seth/add3/jl’ instruction sequence). ‘-msdata=none’ Disable use of the small data area. Variables are put into one of ‘.data’, ‘.bss’, or ‘.rodata’ (unless the ‘section’ attribute has been specified). This is the default. The small data area consists of sections ‘.sdata’ and ‘.sbss’. Objects may be explicitly put in the small data area with the ‘section’ attribute using one of these sections. ‘-msdata=sdata’ Put small global and static data in the small data area, but do not generate special code to reference them. ‘-msdata=use’ Put small global and static data in the small data area, and generate special instructions to reference them. ‘-G NUM’ Put global and static objects less than or equal to NUM bytes into the small data or BSS sections instead of the normal data or BSS sections. The default value of NUM is 8. The ‘-msdata’ option must be set to one of ‘sdata’ or ‘use’ for this option to have any effect. All modules should be compiled with the same ‘-G NUM’ value. Compiling with different values of NUM may or may not work; if it doesn't the linker gives an error message--incorrect code is not generated. ‘-mdebug’ Makes the M32R-specific code in the compiler display some statistics that might help in debugging programs. ‘-malign-loops’ Align all loops to a 32-byte boundary. ‘-mno-align-loops’ Do not enforce a 32-byte alignment for loops. This is the default. ‘-missue-rate=NUMBER’ Issue NUMBER instructions per cycle. NUMBER can only be 1 or 2. ‘-mbranch-cost=NUMBER’ NUMBER can only be 1 or 2. If it is 1 then branches are preferred over conditional code, if it is 2, then the opposite applies. ‘-mflush-trap=NUMBER’ Specifies the trap number to use to flush the cache. The default is 12. Valid numbers are between 0 and 15 inclusive. ‘-mno-flush-trap’ Specifies that the cache cannot be flushed by using a trap. ‘-mflush-func=NAME’ Specifies the name of the operating system function to call to flush the cache. The default is ‘_flush_cache’, but a function call is only used if a trap is not available. ‘-mno-flush-func’ Indicates that there is no OS function for flushing the cache.  File: gcc.info, Node: M680x0 Options, Next: MCore Options, Prev: M32R/D Options, Up: Submodel Options 3.19.25 M680x0 Options ---------------------- These are the ‘-m’ options defined for M680x0 and ColdFire processors. The default settings depend on which architecture was selected when the compiler was configured; the defaults for the most common choices are given below. ‘-march=ARCH’ Generate code for a specific M680x0 or ColdFire instruction set architecture. Permissible values of ARCH for M680x0 architectures are: ‘68000’, ‘68010’, ‘68020’, ‘68030’, ‘68040’, ‘68060’ and ‘cpu32’. ColdFire architectures are selected according to Freescale's ISA classification and the permissible values are: ‘isaa’, ‘isaaplus’, ‘isab’ and ‘isac’. GCC defines a macro ‘__mcfARCH__’ whenever it is generating code for a ColdFire target. The ARCH in this macro is one of the ‘-march’ arguments given above. When used together, ‘-march’ and ‘-mtune’ select code that runs on a family of similar processors but that is optimized for a particular microarchitecture. ‘-mcpu=CPU’ Generate code for a specific M680x0 or ColdFire processor. The M680x0 CPUs are: ‘68000’, ‘68010’, ‘68020’, ‘68030’, ‘68040’, ‘68060’, ‘68302’, ‘68332’ and ‘cpu32’. The ColdFire CPUs are given by the table below, which also classifies the CPUs into families: *Family* *‘-mcpu’ arguments* -------------------------------------------------------------------------- ‘51’ ‘51’ ‘51ac’ ‘51ag’ ‘51cn’ ‘51em’ ‘51je’ ‘51jf’ ‘51jg’ ‘51jm’ ‘51mm’ ‘51qe’ ‘51qm’ ‘5206’ ‘5202’ ‘5204’ ‘5206’ ‘5206e’ ‘5206e’ ‘5208’ ‘5207’ ‘5208’ ‘5211a’ ‘5210a’ ‘5211a’ ‘5213’ ‘5211’ ‘5212’ ‘5213’ ‘5216’ ‘5214’ ‘5216’ ‘52235’ ‘52230’ ‘52231’ ‘52232’ ‘52233’ ‘52234’ ‘52235’ ‘5225’ ‘5224’ ‘5225’ ‘52259’ ‘52252’ ‘52254’ ‘52255’ ‘52256’ ‘52258’ ‘52259’ ‘5235’ ‘5232’ ‘5233’ ‘5234’ ‘5235’ ‘523x’ ‘5249’ ‘5249’ ‘5250’ ‘5250’ ‘5271’ ‘5270’ ‘5271’ ‘5272’ ‘5272’ ‘5275’ ‘5274’ ‘5275’ ‘5282’ ‘5280’ ‘5281’ ‘5282’ ‘528x’ ‘53017’ ‘53011’ ‘53012’ ‘53013’ ‘53014’ ‘53015’ ‘53016’ ‘53017’ ‘5307’ ‘5307’ ‘5329’ ‘5327’ ‘5328’ ‘5329’ ‘532x’ ‘5373’ ‘5372’ ‘5373’ ‘537x’ ‘5407’ ‘5407’ ‘5475’ ‘5470’ ‘5471’ ‘5472’ ‘5473’ ‘5474’ ‘5475’ ‘547x’ ‘5480’ ‘5481’ ‘5482’ ‘5483’ ‘5484’ ‘5485’ ‘-mcpu=CPU’ overrides ‘-march=ARCH’ if ARCH is compatible with CPU. Other combinations of ‘-mcpu’ and ‘-march’ are rejected. GCC defines the macro ‘__mcf_cpu_CPU’ when ColdFire target CPU is selected. It also defines ‘__mcf_family_FAMILY’, where the value of FAMILY is given by the table above. ‘-mtune=TUNE’ Tune the code for a particular microarchitecture within the constraints set by ‘-march’ and ‘-mcpu’. The M680x0 microarchitectures are: ‘68000’, ‘68010’, ‘68020’, ‘68030’, ‘68040’, ‘68060’ and ‘cpu32’. The ColdFire microarchitectures are: ‘cfv1’, ‘cfv2’, ‘cfv3’, ‘cfv4’ and ‘cfv4e’. You can also use ‘-mtune=68020-40’ for code that needs to run relatively well on 68020, 68030 and 68040 targets. ‘-mtune=68020-60’ is similar but includes 68060 targets as well. These two options select the same tuning decisions as ‘-m68020-40’ and ‘-m68020-60’ respectively. GCC defines the macros ‘__mcARCH’ and ‘__mcARCH__’ when tuning for 680x0 architecture ARCH. It also defines ‘mcARCH’ unless either ‘-ansi’ or a non-GNU ‘-std’ option is used. If GCC is tuning for a range of architectures, as selected by ‘-mtune=68020-40’ or ‘-mtune=68020-60’, it defines the macros for every architecture in the range. GCC also defines the macro ‘__mUARCH__’ when tuning for ColdFire microarchitecture UARCH, where UARCH is one of the arguments given above. ‘-m68000’ ‘-mc68000’ Generate output for a 68000. This is the default when the compiler is configured for 68000-based systems. It is equivalent to ‘-march=68000’. Use this option for microcontrollers with a 68000 or EC000 core, including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356. ‘-m68010’ Generate output for a 68010. This is the default when the compiler is configured for 68010-based systems. It is equivalent to ‘-march=68010’. ‘-m68020’ ‘-mc68020’ Generate output for a 68020. This is the default when the compiler is configured for 68020-based systems. It is equivalent to ‘-march=68020’. ‘-m68030’ Generate output for a 68030. This is the default when the compiler is configured for 68030-based systems. It is equivalent to ‘-march=68030’. ‘-m68040’ Generate output for a 68040. This is the default when the compiler is configured for 68040-based systems. It is equivalent to ‘-march=68040’. This option inhibits the use of 68881/68882 instructions that have to be emulated by software on the 68040. Use this option if your 68040 does not have code to emulate those instructions. ‘-m68060’ Generate output for a 68060. This is the default when the compiler is configured for 68060-based systems. It is equivalent to ‘-march=68060’. This option inhibits the use of 68020 and 68881/68882 instructions that have to be emulated by software on the 68060. Use this option if your 68060 does not have code to emulate those instructions. ‘-mcpu32’ Generate output for a CPU32. This is the default when the compiler is configured for CPU32-based systems. It is equivalent to ‘-march=cpu32’. Use this option for microcontrollers with a CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334, 68336, 68340, 68341, 68349 and 68360. ‘-m5200’ Generate output for a 520X ColdFire CPU. This is the default when the compiler is configured for 520X-based systems. It is equivalent to ‘-mcpu=5206’, and is now deprecated in favor of that option. Use this option for microcontroller with a 5200 core, including the MCF5202, MCF5203, MCF5204 and MCF5206. ‘-m5206e’ Generate output for a 5206e ColdFire CPU. The option is now deprecated in favor of the equivalent ‘-mcpu=5206e’. ‘-m528x’ Generate output for a member of the ColdFire 528X family. The option is now deprecated in favor of the equivalent ‘-mcpu=528x’. ‘-m5307’ Generate output for a ColdFire 5307 CPU. The option is now deprecated in favor of the equivalent ‘-mcpu=5307’. ‘-m5407’ Generate output for a ColdFire 5407 CPU. The option is now deprecated in favor of the equivalent ‘-mcpu=5407’. ‘-mcfv4e’ Generate output for a ColdFire V4e family CPU (e.g. 547x/548x). This includes use of hardware floating-point instructions. The option is equivalent to ‘-mcpu=547x’, and is now deprecated in favor of that option. ‘-m68020-40’ Generate output for a 68040, without using any of the new instructions. This results in code that can run relatively efficiently on either a 68020/68881 or a 68030 or a 68040. The generated code does use the 68881 instructions that are emulated on the 68040. The option is equivalent to ‘-march=68020’ ‘-mtune=68020-40’. ‘-m68020-60’ Generate output for a 68060, without using any of the new instructions. This results in code that can run relatively efficiently on either a 68020/68881 or a 68030 or a 68040. The generated code does use the 68881 instructions that are emulated on the 68060. The option is equivalent to ‘-march=68020’ ‘-mtune=68020-60’. ‘-mhard-float’ ‘-m68881’ Generate floating-point instructions. This is the default for 68020 and above, and for ColdFire devices that have an FPU. It defines the macro ‘__HAVE_68881__’ on M680x0 targets and ‘__mcffpu__’ on ColdFire targets. ‘-msoft-float’ Do not generate floating-point instructions; use library calls instead. This is the default for 68000, 68010, and 68832 targets. It is also the default for ColdFire devices that have no FPU. ‘-mdiv’ ‘-mno-div’ Generate (do not generate) ColdFire hardware divide and remainder instructions. If ‘-march’ is used without ‘-mcpu’, the default is "on" for ColdFire architectures and "off" for M680x0 architectures. Otherwise, the default is taken from the target CPU (either the default CPU, or the one specified by ‘-mcpu’). For example, the default is "off" for ‘-mcpu=5206’ and "on" for ‘-mcpu=5206e’. GCC defines the macro ‘__mcfhwdiv__’ when this option is enabled. ‘-mshort’ Consider type ‘int’ to be 16 bits wide, like ‘short int’. Additionally, parameters passed on the stack are also aligned to a 16-bit boundary even on targets whose API mandates promotion to 32-bit. ‘-mno-short’ Do not consider type ‘int’ to be 16 bits wide. This is the default. ‘-mnobitfield’ ‘-mno-bitfield’ Do not use the bit-field instructions. The ‘-m68000’, ‘-mcpu32’ and ‘-m5200’ options imply ‘-mnobitfield’. ‘-mbitfield’ Do use the bit-field instructions. The ‘-m68020’ option implies ‘-mbitfield’. This is the default if you use a configuration designed for a 68020. ‘-mrtd’ Use a different function-calling convention, in which functions that take a fixed number of arguments return with the ‘rtd’ instruction, which pops their arguments while returning. This saves one instruction in the caller since there is no need to pop the arguments there. This calling convention is incompatible with the one normally used on Unix, so you cannot use it if you need to call libraries compiled with the Unix compiler. Also, you must provide function prototypes for all functions that take variable numbers of arguments (including ‘printf’); otherwise incorrect code is generated for calls to those functions. In addition, seriously incorrect code results if you call a function with too many arguments. (Normally, extra arguments are harmlessly ignored.) The ‘rtd’ instruction is supported by the 68010, 68020, 68030, 68040, 68060 and CPU32 processors, but not by the 68000 or 5200. The default is ‘-mno-rtd’. ‘-malign-int’ ‘-mno-align-int’ Control whether GCC aligns ‘int’, ‘long’, ‘long long’, ‘float’, ‘double’, and ‘long double’ variables on a 32-bit boundary (‘-malign-int’) or a 16-bit boundary (‘-mno-align-int’). Aligning variables on 32-bit boundaries produces code that runs somewhat faster on processors with 32-bit busses at the expense of more memory. *Warning:* if you use the ‘-malign-int’ switch, GCC aligns structures containing the above types differently than most published application binary interface specifications for the m68k. Use the pc-relative addressing mode of the 68000 directly, instead of using a global offset table. At present, this option implies ‘-fpic’, allowing at most a 16-bit offset for pc-relative addressing. ‘-fPIC’ is not presently supported with ‘-mpcrel’, though this could be supported for 68020 and higher processors. ‘-mno-strict-align’ ‘-mstrict-align’ Do not (do) assume that unaligned memory references are handled by the system. ‘-msep-data’ Generate code that allows the data segment to be located in a different area of memory from the text segment. This allows for execute-in-place in an environment without virtual memory management. This option implies ‘-fPIC’. ‘-mno-sep-data’ Generate code that assumes that the data segment follows the text segment. This is the default. ‘-mid-shared-library’ Generate code that supports shared libraries via the library ID method. This allows for execute-in-place and shared libraries in an environment without virtual memory management. This option implies ‘-fPIC’. ‘-mno-id-shared-library’ Generate code that doesn't assume ID-based shared libraries are being used. This is the default. ‘-mshared-library-id=n’ Specifies the identification number of the ID-based shared library being compiled. Specifying a value of 0 generates more compact code; specifying other values forces the allocation of that number to the current library, but is no more space- or time-efficient than omitting this option. ‘-mxgot’ ‘-mno-xgot’ When generating position-independent code for ColdFire, generate code that works if the GOT has more than 8192 entries. This code is larger and slower than code generated without this option. On M680x0 processors, this option is not needed; ‘-fPIC’ suffices. GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it only works if the GOT is smaller than about 64k. Anything larger causes the linker to report an error such as: relocation truncated to fit: R_68K_GOT16O foobar If this happens, you should recompile your code with ‘-mxgot’. It should then work with very large GOTs. However, code generated with ‘-mxgot’ is less efficient, since it takes 4 instructions to fetch the value of a global symbol. Note that some linkers, including newer versions of the GNU linker, can create multiple GOTs and sort GOT entries. If you have such a linker, you should only need to use ‘-mxgot’ when compiling a single object file that accesses more than 8192 GOT entries. Very few do. These options have no effect unless GCC is generating position-independent code. ‘-mlong-jump-table-offsets’ Use 32-bit offsets in ‘switch’ tables. The default is to use 16-bit offsets.  File: gcc.info, Node: MCore Options, Next: MicroBlaze Options, Prev: M680x0 Options, Up: Submodel Options 3.19.26 MCore Options --------------------- These are the ‘-m’ options defined for the Motorola M*Core processors. ‘-mhardlit’ ‘-mno-hardlit’ Inline constants into the code stream if it can be done in two instructions or less. ‘-mdiv’ ‘-mno-div’ Use the divide instruction. (Enabled by default). ‘-mrelax-immediate’ ‘-mno-relax-immediate’ Allow arbitrary-sized immediates in bit operations. ‘-mwide-bitfields’ ‘-mno-wide-bitfields’ Always treat bit-fields as ‘int’-sized. ‘-m4byte-functions’ ‘-mno-4byte-functions’ Force all functions to be aligned to a 4-byte boundary. ‘-mcallgraph-data’ ‘-mno-callgraph-data’ Emit callgraph information. ‘-mslow-bytes’ ‘-mno-slow-bytes’ Prefer word access when reading byte quantities. ‘-mlittle-endian’ ‘-mbig-endian’ Generate code for a little-endian target. ‘-m210’ ‘-m340’ Generate code for the 210 processor. ‘-mno-lsim’ Assume that runtime support has been provided and so omit the simulator library (‘libsim.a)’ from the linker command line. ‘-mstack-increment=SIZE’ Set the maximum amount for a single stack increment operation. Large values can increase the speed of programs that contain functions that need a large amount of stack space, but they can also trigger a segmentation fault if the stack is extended too much. The default value is 0x1000.  File: gcc.info, Node: MicroBlaze Options, Next: MIPS Options, Prev: MCore Options, Up: Submodel Options 3.19.27 MicroBlaze Options -------------------------- ‘-msoft-float’ Use software emulation for floating point (default). ‘-mhard-float’ Use hardware floating-point instructions. ‘-mmemcpy’ Do not optimize block moves, use ‘memcpy’. ‘-mno-clearbss’ This option is deprecated. Use ‘-fno-zero-initialized-in-bss’ instead. ‘-mcpu=CPU-TYPE’ Use features of, and schedule code for, the given CPU. Supported values are in the format ‘vX.YY.Z’, where X is a major version, YY is the minor version, and Z is compatibility code. Example values are ‘v3.00.a’, ‘v4.00.b’, ‘v5.00.a’, ‘v5.00.b’, ‘v6.00.a’. ‘-mxl-soft-mul’ Use software multiply emulation (default). ‘-mxl-soft-div’ Use software emulation for divides (default). ‘-mxl-barrel-shift’ Use the hardware barrel shifter. ‘-mxl-pattern-compare’ Use pattern compare instructions. ‘-msmall-divides’ Use table lookup optimization for small signed integer divisions. ‘-mxl-stack-check’ This option is deprecated. Use ‘-fstack-check’ instead. ‘-mxl-gp-opt’ Use GP-relative ‘.sdata’/‘.sbss’ sections. ‘-mxl-multiply-high’ Use multiply high instructions for high part of 32x32 multiply. ‘-mxl-float-convert’ Use hardware floating-point conversion instructions. ‘-mxl-float-sqrt’ Use hardware floating-point square root instruction. ‘-mbig-endian’ Generate code for a big-endian target. ‘-mlittle-endian’ Generate code for a little-endian target. ‘-mxl-reorder’ Use reorder instructions (swap and byte reversed load/store). ‘-mxl-mode-APP-MODEL’ Select application model APP-MODEL. Valid models are ‘executable’ normal executable (default), uses startup code ‘crt0.o’. ‘xmdstub’ for use with Xilinx Microprocessor Debugger (XMD) based software intrusive debug agent called xmdstub. This uses startup file ‘crt1.o’ and sets the start address of the program to 0x800. ‘bootstrap’ for applications that are loaded using a bootloader. This model uses startup file ‘crt2.o’ which does not contain a processor reset vector handler. This is suitable for transferring control on a processor reset to the bootloader rather than the application. ‘novectors’ for applications that do not require any of the MicroBlaze vectors. This option may be useful for applications running within a monitoring application. This model uses ‘crt3.o’ as a startup file. Option ‘-xl-mode-APP-MODEL’ is a deprecated alias for ‘-mxl-mode-APP-MODEL’. ‘-mpic-data-is-text-relative’ Assume that the displacement between the text and data segments is fixed at static link time. This allows data to be referenced by offset from start of text address instead of GOT since PC-relative addressing is not supported.  File: gcc.info, Node: MIPS Options, Next: MMIX Options, Prev: MicroBlaze Options, Up: Submodel Options 3.19.28 MIPS Options -------------------- ‘-EB’ Generate big-endian code. ‘-EL’ Generate little-endian code. This is the default for ‘mips*el-*-*’ configurations. ‘-march=ARCH’ Generate code that runs on ARCH, which can be the name of a generic MIPS ISA, or the name of a particular processor. The ISA names are: ‘mips1’, ‘mips2’, ‘mips3’, ‘mips4’, ‘mips32’, ‘mips32r2’, ‘mips32r3’, ‘mips32r5’, ‘mips32r6’, ‘mips64’, ‘mips64r2’, ‘mips64r3’, ‘mips64r5’ and ‘mips64r6’. The processor names are: ‘4kc’, ‘4km’, ‘4kp’, ‘4ksc’, ‘4kec’, ‘4kem’, ‘4kep’, ‘4ksd’, ‘5kc’, ‘5kf’, ‘20kc’, ‘24kc’, ‘24kf2_1’, ‘24kf1_1’, ‘24kec’, ‘24kef2_1’, ‘24kef1_1’, ‘34kc’, ‘34kf2_1’, ‘34kf1_1’, ‘34kn’, ‘74kc’, ‘74kf2_1’, ‘74kf1_1’, ‘74kf3_2’, ‘1004kc’, ‘1004kf2_1’, ‘1004kf1_1’, ‘i6400’, ‘i6500’, ‘interaptiv’, ‘loongson2e’, ‘loongson2f’, ‘loongson3a’, ‘gs464’, ‘gs464e’, ‘gs264e’, ‘m4k’, ‘m14k’, ‘m14kc’, ‘m14ke’, ‘m14kec’, ‘m5100’, ‘m5101’, ‘octeon’, ‘octeon+’, ‘octeon2’, ‘octeon3’, ‘orion’, ‘p5600’, ‘p6600’, ‘r2000’, ‘r3000’, ‘r3900’, ‘r4000’, ‘r4400’, ‘r4600’, ‘r4650’, ‘r4700’, ‘r5900’, ‘r6000’, ‘r8000’, ‘rm7000’, ‘rm9000’, ‘r10000’, ‘r12000’, ‘r14000’, ‘r16000’, ‘sb1’, ‘sr71000’, ‘vr4100’, ‘vr4111’, ‘vr4120’, ‘vr4130’, ‘vr4300’, ‘vr5000’, ‘vr5400’, ‘vr5500’, ‘xlr’ and ‘xlp’. The special value ‘from-abi’ selects the most compatible architecture for the selected ABI (that is, ‘mips1’ for 32-bit ABIs and ‘mips3’ for 64-bit ABIs). The native Linux/GNU toolchain also supports the value ‘native’, which selects the best architecture option for the host processor. ‘-march=native’ has no effect if GCC does not recognize the processor. In processor names, a final ‘000’ can be abbreviated as ‘k’ (for example, ‘-march=r2k’). Prefixes are optional, and ‘vr’ may be written ‘r’. Names of the form ‘Nf2_1’ refer to processors with FPUs clocked at half the rate of the core, names of the form ‘Nf1_1’ refer to processors with FPUs clocked at the same rate as the core, and names of the form ‘Nf3_2’ refer to processors with FPUs clocked a ratio of 3:2 with respect to the core. For compatibility reasons, ‘Nf’ is accepted as a synonym for ‘Nf2_1’ while ‘Nx’ and ‘Bfx’ are accepted as synonyms for ‘Nf1_1’. GCC defines two macros based on the value of this option. The first is ‘_MIPS_ARCH’, which gives the name of target architecture, as a string. The second has the form ‘_MIPS_ARCH_FOO’, where FOO is the capitalized value of ‘_MIPS_ARCH’. For example, ‘-march=r2000’ sets ‘_MIPS_ARCH’ to ‘"r2000"’ and defines the macro ‘_MIPS_ARCH_R2000’. Note that the ‘_MIPS_ARCH’ macro uses the processor names given above. In other words, it has the full prefix and does not abbreviate ‘000’ as ‘k’. In the case of ‘from-abi’, the macro names the resolved architecture (either ‘"mips1"’ or ‘"mips3"’). It names the default architecture when no ‘-march’ option is given. ‘-mtune=ARCH’ Optimize for ARCH. Among other things, this option controls the way instructions are scheduled, and the perceived cost of arithmetic operations. The list of ARCH values is the same as for ‘-march’. When this option is not used, GCC optimizes for the processor specified by ‘-march’. By using ‘-march’ and ‘-mtune’ together, it is possible to generate code that runs on a family of processors, but optimize the code for one particular member of that family. ‘-mtune’ defines the macros ‘_MIPS_TUNE’ and ‘_MIPS_TUNE_FOO’, which work in the same way as the ‘-march’ ones described above. ‘-mips1’ Equivalent to ‘-march=mips1’. ‘-mips2’ Equivalent to ‘-march=mips2’. ‘-mips3’ Equivalent to ‘-march=mips3’. ‘-mips4’ Equivalent to ‘-march=mips4’. ‘-mips32’ Equivalent to ‘-march=mips32’. ‘-mips32r3’ Equivalent to ‘-march=mips32r3’. ‘-mips32r5’ Equivalent to ‘-march=mips32r5’. ‘-mips32r6’ Equivalent to ‘-march=mips32r6’. ‘-mips64’ Equivalent to ‘-march=mips64’. ‘-mips64r2’ Equivalent to ‘-march=mips64r2’. ‘-mips64r3’ Equivalent to ‘-march=mips64r3’. ‘-mips64r5’ Equivalent to ‘-march=mips64r5’. ‘-mips64r6’ Equivalent to ‘-march=mips64r6’. ‘-mips16’ ‘-mno-mips16’ Generate (do not generate) MIPS16 code. If GCC is targeting a MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE. MIPS16 code generation can also be controlled on a per-function basis by means of ‘mips16’ and ‘nomips16’ attributes. *Note Function Attributes::, for more information. ‘-mmips16e2’ ‘-mno-mips16e2’ Use (do not use) the MIPS16e2 ASE. This option modifies the behavior of the ‘-mips16’ option such that it targets the MIPS16e2 ASE. ‘-mflip-mips16’ Generate MIPS16 code on alternating functions. This option is provided for regression testing of mixed MIPS16/non-MIPS16 code generation, and is not intended for ordinary use in compiling user code. ‘-minterlink-compressed’ ‘-mno-interlink-compressed’ Require (do not require) that code using the standard (uncompressed) MIPS ISA be link-compatible with MIPS16 and microMIPS code, and vice versa. For example, code using the standard ISA encoding cannot jump directly to MIPS16 or microMIPS code; it must either use a call or an indirect jump. ‘-minterlink-compressed’ therefore disables direct jumps unless GCC knows that the target of the jump is not compressed. ‘-minterlink-mips16’ ‘-mno-interlink-mips16’ Aliases of ‘-minterlink-compressed’ and ‘-mno-interlink-compressed’. These options predate the microMIPS ASE and are retained for backwards compatibility. ‘-mabi=32’ ‘-mabi=o64’ ‘-mabi=n32’ ‘-mabi=64’ ‘-mabi=eabi’ Generate code for the given ABI. Note that the EABI has a 32-bit and a 64-bit variant. GCC normally generates 64-bit code when you select a 64-bit architecture, but you can use ‘-mgp32’ to get 32-bit code instead. For information about the O64 ABI, see . GCC supports a variant of the o32 ABI in which floating-point registers are 64 rather than 32 bits wide. You can select this combination with ‘-mabi=32’ ‘-mfp64’. This ABI relies on the ‘mthc1’ and ‘mfhc1’ instructions and is therefore only supported for MIPS32R2, MIPS32R3 and MIPS32R5 processors. The register assignments for arguments and return values remain the same, but each scalar value is passed in a single 64-bit register rather than a pair of 32-bit registers. For example, scalar floating-point values are returned in ‘$f0’ only, not a ‘$f0’/‘$f1’ pair. The set of call-saved registers also remains the same in that the even-numbered double-precision registers are saved. Two additional variants of the o32 ABI are supported to enable a transition from 32-bit to 64-bit registers. These are FPXX (‘-mfpxx’) and FP64A (‘-mfp64’ ‘-mno-odd-spreg’). The FPXX extension mandates that all code must execute correctly when run using 32-bit or 64-bit registers. The code can be interlinked with either FP32 or FP64, but not both. The FP64A extension is similar to the FP64 extension but forbids the use of odd-numbered single-precision registers. This can be used in conjunction with the ‘FRE’ mode of FPUs in MIPS32R5 processors and allows both FP32 and FP64A code to interlink and run in the same process without changing FPU modes. ‘-mabicalls’ ‘-mno-abicalls’ Generate (do not generate) code that is suitable for SVR4-style dynamic objects. ‘-mabicalls’ is the default for SVR4-based systems. ‘-mshared’ ‘-mno-shared’ Generate (do not generate) code that is fully position-independent, and that can therefore be linked into shared libraries. This option only affects ‘-mabicalls’. All ‘-mabicalls’ code has traditionally been position-independent, regardless of options like ‘-fPIC’ and ‘-fpic’. However, as an extension, the GNU toolchain allows executables to use absolute accesses for locally-binding symbols. It can also use shorter GP initialization sequences and generate direct calls to locally-defined functions. This mode is selected by ‘-mno-shared’. ‘-mno-shared’ depends on binutils 2.16 or higher and generates objects that can only be linked by the GNU linker. However, the option does not affect the ABI of the final executable; it only affects the ABI of relocatable objects. Using ‘-mno-shared’ generally makes executables both smaller and quicker. ‘-mshared’ is the default. ‘-mplt’ ‘-mno-plt’ Assume (do not assume) that the static and dynamic linkers support PLTs and copy relocations. This option only affects ‘-mno-shared -mabicalls’. For the n64 ABI, this option has no effect without ‘-msym32’. You can make ‘-mplt’ the default by configuring GCC with ‘--with-mips-plt’. The default is ‘-mno-plt’ otherwise. ‘-mxgot’ ‘-mno-xgot’ Lift (do not lift) the usual restrictions on the size of the global offset table. GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it only works if the GOT is smaller than about 64k. Anything larger causes the linker to report an error such as: relocation truncated to fit: R_MIPS_GOT16 foobar If this happens, you should recompile your code with ‘-mxgot’. This works with very large GOTs, although the code is also less efficient, since it takes three instructions to fetch the value of a global symbol. Note that some linkers can create multiple GOTs. If you have such a linker, you should only need to use ‘-mxgot’ when a single object file accesses more than 64k's worth of GOT entries. Very few do. These options have no effect unless GCC is generating position independent code. ‘-mgp32’ Assume that general-purpose registers are 32 bits wide. ‘-mgp64’ Assume that general-purpose registers are 64 bits wide. ‘-mfp32’ Assume that floating-point registers are 32 bits wide. ‘-mfp64’ Assume that floating-point registers are 64 bits wide. ‘-mfpxx’ Do not assume the width of floating-point registers. ‘-mhard-float’ Use floating-point coprocessor instructions. ‘-msoft-float’ Do not use floating-point coprocessor instructions. Implement floating-point calculations using library calls instead. ‘-mno-float’ Equivalent to ‘-msoft-float’, but additionally asserts that the program being compiled does not perform any floating-point operations. This option is presently supported only by some bare-metal MIPS configurations, where it may select a special set of libraries that lack all floating-point support (including, for example, the floating-point ‘printf’ formats). If code compiled with ‘-mno-float’ accidentally contains floating-point operations, it is likely to suffer a link-time or run-time failure. ‘-msingle-float’ Assume that the floating-point coprocessor only supports single-precision operations. ‘-mdouble-float’ Assume that the floating-point coprocessor supports double-precision operations. This is the default. ‘-modd-spreg’ ‘-mno-odd-spreg’ Enable the use of odd-numbered single-precision floating-point registers for the o32 ABI. This is the default for processors that are known to support these registers. When using the o32 FPXX ABI, ‘-mno-odd-spreg’ is set by default. ‘-mabs=2008’ ‘-mabs=legacy’ These options control the treatment of the special not-a-number (NaN) IEEE 754 floating-point data with the ‘abs.fmt’ and ‘neg.fmt’ machine instructions. By default or when ‘-mabs=legacy’ is used the legacy treatment is selected. In this case these instructions are considered arithmetic and avoided where correct operation is required and the input operand might be a NaN. A longer sequence of instructions that manipulate the sign bit of floating-point datum manually is used instead unless the ‘-ffinite-math-only’ option has also been specified. The ‘-mabs=2008’ option selects the IEEE 754-2008 treatment. In this case these instructions are considered non-arithmetic and therefore operating correctly in all cases, including in particular where the input operand is a NaN. These instructions are therefore always used for the respective operations. ‘-mnan=2008’ ‘-mnan=legacy’ These options control the encoding of the special not-a-number (NaN) IEEE 754 floating-point data. The ‘-mnan=legacy’ option selects the legacy encoding. In this case quiet NaNs (qNaNs) are denoted by the first bit of their trailing significand field being 0, whereas signaling NaNs (sNaNs) are denoted by the first bit of their trailing significand field being 1. The ‘-mnan=2008’ option selects the IEEE 754-2008 encoding. In this case qNaNs are denoted by the first bit of their trailing significand field being 1, whereas sNaNs are denoted by the first bit of their trailing significand field being 0. The default is ‘-mnan=legacy’ unless GCC has been configured with ‘--with-nan=2008’. ‘-mllsc’ ‘-mno-llsc’ Use (do not use) ‘ll’, ‘sc’, and ‘sync’ instructions to implement atomic memory built-in functions. When neither option is specified, GCC uses the instructions if the target architecture supports them. ‘-mllsc’ is useful if the runtime environment can emulate the instructions and ‘-mno-llsc’ can be useful when compiling for nonstandard ISAs. You can make either option the default by configuring GCC with ‘--with-llsc’ and ‘--without-llsc’ respectively. ‘--with-llsc’ is the default for some configurations; see the installation documentation for details. ‘-mdsp’ ‘-mno-dsp’ Use (do not use) revision 1 of the MIPS DSP ASE. *Note MIPS DSP Built-in Functions::. This option defines the preprocessor macro ‘__mips_dsp’. It also defines ‘__mips_dsp_rev’ to 1. ‘-mdspr2’ ‘-mno-dspr2’ Use (do not use) revision 2 of the MIPS DSP ASE. *Note MIPS DSP Built-in Functions::. This option defines the preprocessor macros ‘__mips_dsp’ and ‘__mips_dspr2’. It also defines ‘__mips_dsp_rev’ to 2. ‘-msmartmips’ ‘-mno-smartmips’ Use (do not use) the MIPS SmartMIPS ASE. ‘-mpaired-single’ ‘-mno-paired-single’ Use (do not use) paired-single floating-point instructions. *Note MIPS Paired-Single Support::. This option requires hardware floating-point support to be enabled. ‘-mdmx’ ‘-mno-mdmx’ Use (do not use) MIPS Digital Media Extension instructions. This option can only be used when generating 64-bit code and requires hardware floating-point support to be enabled. ‘-mips3d’ ‘-mno-mips3d’ Use (do not use) the MIPS-3D ASE. *Note MIPS-3D Built-in Functions::. The option ‘-mips3d’ implies ‘-mpaired-single’. ‘-mmicromips’ ‘-mno-micromips’ Generate (do not generate) microMIPS code. MicroMIPS code generation can also be controlled on a per-function basis by means of ‘micromips’ and ‘nomicromips’ attributes. *Note Function Attributes::, for more information. ‘-mmt’ ‘-mno-mt’ Use (do not use) MT Multithreading instructions. ‘-mmcu’ ‘-mno-mcu’ Use (do not use) the MIPS MCU ASE instructions. ‘-meva’ ‘-mno-eva’ Use (do not use) the MIPS Enhanced Virtual Addressing instructions. ‘-mvirt’ ‘-mno-virt’ Use (do not use) the MIPS Virtualization (VZ) instructions. ‘-mxpa’ ‘-mno-xpa’ Use (do not use) the MIPS eXtended Physical Address (XPA) instructions. ‘-mcrc’ ‘-mno-crc’ Use (do not use) the MIPS Cyclic Redundancy Check (CRC) instructions. ‘-mginv’ ‘-mno-ginv’ Use (do not use) the MIPS Global INValidate (GINV) instructions. ‘-mloongson-mmi’ ‘-mno-loongson-mmi’ Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI). ‘-mloongson-ext’ ‘-mno-loongson-ext’ Use (do not use) the MIPS Loongson EXTensions (EXT) instructions. ‘-mloongson-ext2’ ‘-mno-loongson-ext2’ Use (do not use) the MIPS Loongson EXTensions r2 (EXT2) instructions. ‘-mlong64’ Force ‘long’ types to be 64 bits wide. See ‘-mlong32’ for an explanation of the default and the way that the pointer size is determined. ‘-mlong32’ Force ‘long’, ‘int’, and pointer types to be 32 bits wide. The default size of ‘int’s, ‘long’s and pointers depends on the ABI. All the supported ABIs use 32-bit ‘int’s. The n64 ABI uses 64-bit ‘long’s, as does the 64-bit EABI; the others use 32-bit ‘long’s. Pointers are the same size as ‘long’s, or the same size as integer registers, whichever is smaller. ‘-msym32’ ‘-mno-sym32’ Assume (do not assume) that all symbols have 32-bit values, regardless of the selected ABI. This option is useful in combination with ‘-mabi=64’ and ‘-mno-abicalls’ because it allows GCC to generate shorter and faster references to symbolic addresses. ‘-G NUM’ Put definitions of externally-visible data in a small data section if that data is no bigger than NUM bytes. GCC can then generate more efficient accesses to the data; see ‘-mgpopt’ for details. The default ‘-G’ option depends on the configuration. ‘-mlocal-sdata’ ‘-mno-local-sdata’ Extend (do not extend) the ‘-G’ behavior to local data too, such as to static variables in C. ‘-mlocal-sdata’ is the default for all configurations. If the linker complains that an application is using too much small data, you might want to try rebuilding the less performance-critical parts with ‘-mno-local-sdata’. You might also want to build large libraries with ‘-mno-local-sdata’, so that the libraries leave more room for the main program. ‘-mextern-sdata’ ‘-mno-extern-sdata’ Assume (do not assume) that externally-defined data is in a small data section if the size of that data is within the ‘-G’ limit. ‘-mextern-sdata’ is the default for all configurations. If you compile a module MOD with ‘-mextern-sdata’ ‘-G NUM’ ‘-mgpopt’, and MOD references a variable VAR that is no bigger than NUM bytes, you must make sure that VAR is placed in a small data section. If VAR is defined by another module, you must either compile that module with a high-enough ‘-G’ setting or attach a ‘section’ attribute to VAR's definition. If VAR is common, you must link the application with a high-enough ‘-G’ setting. The easiest way of satisfying these restrictions is to compile and link every module with the same ‘-G’ option. However, you may wish to build a library that supports several different small data limits. You can do this by compiling the library with the highest supported ‘-G’ setting and additionally using ‘-mno-extern-sdata’ to stop the library from making assumptions about externally-defined data. ‘-mgpopt’ ‘-mno-gpopt’ Use (do not use) GP-relative accesses for symbols that are known to be in a small data section; see ‘-G’, ‘-mlocal-sdata’ and ‘-mextern-sdata’. ‘-mgpopt’ is the default for all configurations. ‘-mno-gpopt’ is useful for cases where the ‘$gp’ register might not hold the value of ‘_gp’. For example, if the code is part of a library that might be used in a boot monitor, programs that call boot monitor routines pass an unknown value in ‘$gp’. (In such situations, the boot monitor itself is usually compiled with ‘-G0’.) ‘-mno-gpopt’ implies ‘-mno-local-sdata’ and ‘-mno-extern-sdata’. ‘-membedded-data’ ‘-mno-embedded-data’ Allocate variables to the read-only data section first if possible, then next in the small data section if possible, otherwise in data. This gives slightly slower code than the default, but reduces the amount of RAM required when executing, and thus may be preferred for some embedded systems. ‘-muninit-const-in-rodata’ ‘-mno-uninit-const-in-rodata’ Put uninitialized ‘const’ variables in the read-only data section. This option is only meaningful in conjunction with ‘-membedded-data’. ‘-mcode-readable=SETTING’ Specify whether GCC may generate code that reads from executable sections. There are three possible settings: ‘-mcode-readable=yes’ Instructions may freely access executable sections. This is the default setting. ‘-mcode-readable=pcrel’ MIPS16 PC-relative load instructions can access executable sections, but other instructions must not do so. This option is useful on 4KSc and 4KSd processors when the code TLBs have the Read Inhibit bit set. It is also useful on processors that can be configured to have a dual instruction/data SRAM interface and that, like the M4K, automatically redirect PC-relative loads to the instruction RAM. ‘-mcode-readable=no’ Instructions must not access executable sections. This option can be useful on targets that are configured to have a dual instruction/data SRAM interface but that (unlike the M4K) do not automatically redirect PC-relative loads to the instruction RAM. ‘-msplit-addresses’ ‘-mno-split-addresses’ Enable (disable) use of the ‘%hi()’ and ‘%lo()’ assembler relocation operators. This option has been superseded by ‘-mexplicit-relocs’ but is retained for backwards compatibility. ‘-mexplicit-relocs=none’ ‘-mexplicit-relocs=base’ ‘-mexplicit-relocs=pcrel’ ‘-mexplicit-relocs’ ‘-mno-explicit-relocs’ These options control whether explicit relocs (such as %gp_rel) are used. The default value depends on the version of GAS when GCC itself was built. The ‘base’ explicit-relocs support introdunced into GAS in 2001. The ‘pcrel’ explicit-relocs support introdunced into GAS in 2014, which supports ‘%pcrel_hi’ and ‘%pcrel_lo’. ‘-mcheck-zero-division’ ‘-mno-check-zero-division’ Trap (do not trap) on integer division by zero. The default is ‘-mcheck-zero-division’. ‘-mdivide-traps’ ‘-mdivide-breaks’ MIPS systems check for division by zero by generating either a conditional trap or a break instruction. Using traps results in smaller code, but is only supported on MIPS II and later. Also, some versions of the Linux kernel have a bug that prevents trap from generating the proper signal (‘SIGFPE’). Use ‘-mdivide-traps’ to allow conditional traps on architectures that support them and ‘-mdivide-breaks’ to force the use of breaks. The default is usually ‘-mdivide-traps’, but this can be overridden at configure time using ‘--with-divide=breaks’. Divide-by-zero checks can be completely disabled using ‘-mno-check-zero-division’. ‘-mload-store-pairs’ ‘-mno-load-store-pairs’ Enable (disable) an optimization that pairs consecutive load or store instructions to enable load/store bonding. This option is enabled by default but only takes effect when the selected architecture is known to support bonding. ‘-munaligned-access’ ‘-mno-unaligned-access’ Enable (disable) direct unaligned access for MIPS Release 6. MIPSr6 requires load/store unaligned-access support, by hardware or trap&emulate. So ‘-mno-unaligned-access’ may be needed by kernel. ‘-mmemcpy’ ‘-mno-memcpy’ Force (do not force) the use of ‘memcpy’ for non-trivial block moves. The default is ‘-mno-memcpy’, which allows GCC to inline most constant-sized copies. ‘-mlong-calls’ ‘-mno-long-calls’ Disable (do not disable) use of the ‘jal’ instruction. Calling functions using ‘jal’ is more efficient but requires the caller and callee to be in the same 256 megabyte segment. This option has no effect on abicalls code. The default is ‘-mno-long-calls’. ‘-mmad’ ‘-mno-mad’ Enable (disable) use of the ‘mad’, ‘madu’ and ‘mul’ instructions, as provided by the R4650 ISA. ‘-mimadd’ ‘-mno-imadd’ Enable (disable) use of the ‘madd’ and ‘msub’ integer instructions. The default is ‘-mimadd’ on architectures that support ‘madd’ and ‘msub’ except for the 74k architecture where it was found to generate slower code. ‘-mfused-madd’ ‘-mno-fused-madd’ Enable (disable) use of the floating-point multiply-accumulate instructions, when they are available. The default is ‘-mfused-madd’. On the R8000 CPU when multiply-accumulate instructions are used, the intermediate product is calculated to infinite precision and is not subject to the FCSR Flush to Zero bit. This may be undesirable in some circumstances. On other processors the result is numerically identical to the equivalent computation using separate multiply, add, subtract and negate instructions. ‘-nocpp’ Tell the MIPS assembler to not run its preprocessor over user assembler files (with a ‘.s’ suffix) when assembling them. ‘-mfix-24k’ ‘-mno-fix-24k’ Work around the 24K E48 (lost data on stores during refill) errata. The workarounds are implemented by the assembler rather than by GCC. ‘-mfix-r4000’ ‘-mno-fix-r4000’ Work around certain R4000 CPU errata: − A double-word or a variable shift may give an incorrect result if executed immediately after starting an integer division. − A double-word or a variable shift may give an incorrect result if executed while an integer multiplication is in progress. − An integer division may give an incorrect result if started in a delay slot of a taken branch or a jump. ‘-mfix-r4400’ ‘-mno-fix-r4400’ Work around certain R4400 CPU errata: − A double-word or a variable shift may give an incorrect result if executed immediately after starting an integer division. ‘-mfix-r10000’ ‘-mno-fix-r10000’ Work around certain R10000 errata: − ‘ll’/‘sc’ sequences may not behave atomically on revisions prior to 3.0. They may deadlock on revisions 2.6 and earlier. This option can only be used if the target architecture supports branch-likely instructions. ‘-mfix-r10000’ is the default when ‘-march=r10000’ is used; ‘-mno-fix-r10000’ is the default otherwise. ‘-mfix-r5900’ ‘-mno-fix-r5900’ Do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer and always schedule a ‘nop’ instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. The workaround is implemented by the assembler rather than by GCC. ‘-mfix-rm7000’ ‘-mno-fix-rm7000’ Work around the RM7000 ‘dmult’/‘dmultu’ errata. The workarounds are implemented by the assembler rather than by GCC. ‘-mfix-vr4120’ ‘-mno-fix-vr4120’ Work around certain VR4120 errata: − ‘dmultu’ does not always produce the correct result. − ‘div’ and ‘ddiv’ do not always produce the correct result if one of the operands is negative. The workarounds for the division errata rely on special functions in ‘libgcc.a’. At present, these functions are only provided by the ‘mips64vr*-elf’ configurations. Other VR4120 errata require a NOP to be inserted between certain pairs of instructions. These errata are handled by the assembler, not by GCC itself. ‘-mfix-vr4130’ Work around the VR4130 ‘mflo’/‘mfhi’ errata. The workarounds are implemented by the assembler rather than by GCC, although GCC avoids using ‘mflo’ and ‘mfhi’ if the VR4130 ‘macc’, ‘macchi’, ‘dmacc’ and ‘dmacchi’ instructions are available instead. ‘-mfix-sb1’ ‘-mno-fix-sb1’ Work around certain SB-1 CPU core errata. (This flag currently works around the SB-1 revision 2 "F1" and "F2" floating-point errata.) ‘-mr10k-cache-barrier=SETTING’ Specify whether GCC should insert cache barriers to avoid the side effects of speculation on R10K processors. In common with many processors, the R10K tries to predict the outcome of a conditional branch and speculatively executes instructions from the "taken" branch. It later aborts these instructions if the predicted outcome is wrong. However, on the R10K, even aborted instructions can have side effects. This problem only affects kernel stores and, depending on the system, kernel loads. As an example, a speculatively-executed store may load the target memory into cache and mark the cache line as dirty, even if the store itself is later aborted. If a DMA operation writes to the same area of memory before the "dirty" line is flushed, the cached data overwrites the DMA-ed data. See the R10K processor manual for a full description, including other potential problems. One workaround is to insert cache barrier instructions before every memory access that might be speculatively executed and that might have side effects even if aborted. ‘-mr10k-cache-barrier=SETTING’ controls GCC's implementation of this workaround. It assumes that aborted accesses to any byte in the following regions does not have side effects: 1. the memory occupied by the current function's stack frame; 2. the memory occupied by an incoming stack argument; 3. the memory occupied by an object with a link-time-constant address. It is the kernel's responsibility to ensure that speculative accesses to these regions are indeed safe. If the input program contains a function declaration such as: void foo (void); then the implementation of ‘foo’ must allow ‘j foo’ and ‘jal foo’ to be executed speculatively. GCC honors this restriction for functions it compiles itself. It expects non-GCC functions (such as hand-written assembly code) to do the same. The option has three forms: ‘-mr10k-cache-barrier=load-store’ Insert a cache barrier before a load or store that might be speculatively executed and that might have side effects even if aborted. ‘-mr10k-cache-barrier=store’ Insert a cache barrier before a store that might be speculatively executed and that might have side effects even if aborted. ‘-mr10k-cache-barrier=none’ Disable the insertion of cache barriers. This is the default setting. ‘-mflush-func=FUNC’ ‘-mno-flush-func’ Specifies the function to call to flush the I and D caches, or to not call any such function. If called, the function must take the same arguments as the common ‘_flush_func’, that is, the address of the memory range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both caches). The default depends on the target GCC was configured for, but commonly is either ‘_flush_func’ or ‘__cpu_flush’. ‘mbranch-cost=NUM’ Set the cost of branches to roughly NUM "simple" instructions. This cost is only a heuristic and is not guaranteed to produce consistent results across releases. A zero cost redundantly selects the default, which is based on the ‘-mtune’ setting. ‘-mbranch-likely’ ‘-mno-branch-likely’ Enable or disable use of Branch Likely instructions, regardless of the default for the selected architecture. By default, Branch Likely instructions may be generated if they are supported by the selected architecture. An exception is for the MIPS32 and MIPS64 architectures and processors that implement those architectures; for those, Branch Likely instructions are not be generated by default because the MIPS32 and MIPS64 architectures specifically deprecate their use. ‘-mcompact-branches=never’ ‘-mcompact-branches=optimal’ ‘-mcompact-branches=always’ These options control which form of branches will be generated. The default is ‘-mcompact-branches=optimal’. The ‘-mcompact-branches=never’ option ensures that compact branch instructions will never be generated. The ‘-mcompact-branches=always’ option ensures that a compact branch instruction will be generated if available for MIPS Release 6 onwards. If a compact branch instruction is not available (or pre-R6), a delay slot form of the branch will be used instead. If it is used for MIPS16/microMIPS targets, it will be just ignored now. The behaviour for MIPS16/microMIPS may change in future, since they do have some compact branch instructions. The ‘-mcompact-branches=optimal’ option will cause a delay slot branch to be used if one is available in the current ISA and the delay slot is successfully filled. If the delay slot is not filled, a compact branch will be chosen if one is available. ‘-mfp-exceptions’ ‘-mno-fp-exceptions’ Specifies whether FP exceptions are enabled. This affects how FP instructions are scheduled for some processors. The default is that FP exceptions are enabled. For instance, on the SB-1, if FP exceptions are disabled, and we are emitting 64-bit code, then we can use both FP pipes. Otherwise, we can only use one FP pipe. ‘-mvr4130-align’ ‘-mno-vr4130-align’ The VR4130 pipeline is two-way superscalar, but can only issue two instructions together if the first one is 8-byte aligned. When this option is enabled, GCC aligns pairs of instructions that it thinks should execute in parallel. This option only has an effect when optimizing for the VR4130. It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level ‘-O3’. ‘-msynci’ ‘-mno-synci’ Enable (disable) generation of ‘synci’ instructions on architectures that support it. The ‘synci’ instructions (if enabled) are generated when ‘__builtin___clear_cache’ is compiled. This option defaults to ‘-mno-synci’, but the default can be overridden by configuring GCC with ‘--with-synci’. When compiling code for single processor systems, it is generally safe to use ‘synci’. However, on many multi-core (SMP) systems, it does not invalidate the instruction caches on all cores and may lead to undefined behavior. ‘-mrelax-pic-calls’ ‘-mno-relax-pic-calls’ Try to turn PIC calls that are normally dispatched via register ‘$25’ into direct calls. This is only possible if the linker can resolve the destination at link time and if the destination is within range for a direct call. ‘-mrelax-pic-calls’ is the default if GCC was configured to use an assembler and a linker that support the ‘.reloc’ assembly directive and ‘-mexplicit-relocs’ is in effect. With ‘-mno-explicit-relocs’, this optimization can be performed by the assembler and the linker alone without help from the compiler. ‘-mmcount-ra-address’ ‘-mno-mcount-ra-address’ Emit (do not emit) code that allows ‘_mcount’ to modify the calling function's return address. When enabled, this option extends the usual ‘_mcount’ interface with a new RA-ADDRESS parameter, which has type ‘intptr_t *’ and is passed in register ‘$12’. ‘_mcount’ can then modify the return address by doing both of the following: • Returning the new address in register ‘$31’. • Storing the new address in ‘*RA-ADDRESS’, if RA-ADDRESS is nonnull. The default is ‘-mno-mcount-ra-address’. ‘-mframe-header-opt’ ‘-mno-frame-header-opt’ Enable (disable) frame header optimization in the o32 ABI. When using the o32 ABI, calling functions will allocate 16 bytes on the stack for the called function to write out register arguments. When enabled, this optimization will suppress the allocation of the frame header if it can be determined that it is unused. This optimization is off by default at all optimization levels. ‘-mlxc1-sxc1’ ‘-mno-lxc1-sxc1’ When applicable, enable (disable) the generation of ‘lwxc1’, ‘swxc1’, ‘ldxc1’, ‘sdxc1’ instructions. Enabled by default. ‘-mmadd4’ ‘-mno-madd4’ When applicable, enable (disable) the generation of 4-operand ‘madd.s’, ‘madd.d’ and related instructions. Enabled by default.  File: gcc.info, Node: MMIX Options, Next: MN10300 Options, Prev: MIPS Options, Up: Submodel Options 3.19.29 MMIX Options -------------------- These options are defined for the MMIX: ‘-mlibfuncs’ ‘-mno-libfuncs’ Specify that intrinsic library functions are being compiled, passing all values in registers, no matter the size. ‘-mepsilon’ ‘-mno-epsilon’ Generate floating-point comparison instructions that compare with respect to the ‘rE’ epsilon register. ‘-mabi=mmixware’ ‘-mabi=gnu’ Generate code that passes function parameters and return values that (in the called function) are seen as registers ‘$0’ and up, as opposed to the GNU ABI which uses global registers ‘$231’ and up. ‘-mzero-extend’ ‘-mno-zero-extend’ When reading data from memory in sizes shorter than 64 bits, use (do not use) zero-extending load instructions by default, rather than sign-extending ones. ‘-mknuthdiv’ ‘-mno-knuthdiv’ Make the result of a division yielding a remainder have the same sign as the divisor. With the default, ‘-mno-knuthdiv’, the sign of the remainder follows the sign of the dividend. Both methods are arithmetically valid, the latter being almost exclusively used. ‘-mtoplevel-symbols’ ‘-mno-toplevel-symbols’ Prepend (do not prepend) a ‘:’ to all global symbols, so the assembly code can be used with the ‘PREFIX’ assembly directive. ‘-melf’ Generate an executable in the ELF format, rather than the default ‘mmo’ format used by the ‘mmix’ simulator. ‘-mbranch-predict’ ‘-mno-branch-predict’ Use (do not use) the probable-branch instructions, when static branch prediction indicates a probable branch. ‘-mbase-addresses’ ‘-mno-base-addresses’ Generate (do not generate) code that uses _base addresses_. Using a base address automatically generates a request (handled by the assembler and the linker) for a constant to be set up in a global register. The register is used for one or more base address requests within the range 0 to 255 from the value held in the register. The generally leads to short and fast code, but the number of different data items that can be addressed is limited. This means that a program that uses lots of static data may require ‘-mno-base-addresses’. ‘-msingle-exit’ ‘-mno-single-exit’ Force (do not force) generated code to have a single exit point in each function.